| General Sessions | |||
| Wednesday, July 12, 2017 | |||
| 9:00 am - 10:15 am | Grand Ballroom | Welcome & Keynote [More Info] Ramadas Rajagopal, Synopsys Dr. Aart De Geus, Synopsys | |
| Implementation | |||
| Wednesday, July 12, 2017 | |||
| 10:30 am - 11:30 am | Royal Ballroom | Best Practices for High-Performance, Energy Efficient Implementations of the Latest ARM® Processors in 16-Nanometer FinFET Compact (16FFC) Process Technology using the Synopsys Galaxy™ Design Platform [More Info] Shardul Kalamkar, ARM Harissh Swaminathan, Synopsys | |
| 11:30 am - 12:00 pm | Royal Ballroom | Hierarchical Implementation of a High-Performance CPU using ICC II: A Case Study [More Info] Francis Chockalingam, Broadcom Sreenath Ramakrishna, Broadcom | |
| 12:00 pm - 12:30 pm | Royal Ballroom | Optimization Strategies for Faster and Better QoR at Lower Technology Nodes [More Info] Sajeesh Ammikkallingal, AMD Mohini Polimetla, AMD Shanmugapriya Murugesan, AMD Sreedhara Khayadada, Synopsys | |
| 1:30 pm - 2:00 pm | Royal Ballroom | PNR Flow Customization for the Implementation of High Speed Cores [More Info] Prashant Aggarwal, Qualcomm Santosh KT, Qualcomm Sagar Patel, Qualcomm Ujjwal Prakash, Qualcomm | |
| 2:00 pm - 2:30 pm | Royal Ballroom | A Systematic Approach for Physical Implementation of Ultra-High Speed Intra Die Scalable Coherent Interface for High Performance/Complex SoCs [More Info] | |
| 2:30 pm - 3:00 pm | Royal Ballroom | Design Complexity Beyond: Multi-Million, High Frequency, Advanced Node - using IC Compiler II [More Info] Rajeev Singh, MediaTek | |
| 3:30 pm - 4:00 pm | Royal Ballroom | Formality Challenges for Low Power Based Flow for Multimillion Gate Complex SoCs [More Info] Abhijeet Kumar, Broadcom Govind Sreekumar, Broadcom Richa Soni, Synopsys | |
| 4:00 pm - 5:00 pm | Royal Ballroom | Getting the Best Out from Design Compiler Graphical [More Info] Philip Issac, Synopsys | |
| Networking Opportunities | |||
| Wednesday, July 12, 2017 | |||
| 7:30 am - 8:45 am | Lobby Garden | Registration and Breakfast | |
| 10:15 am - 10:30 am | Pre-Function Area | Break | |
| 12:30 pm - 1:30 pm | Pre-Function Area | Networking Lunch | |
| 3:15 pm - 3:30 pm | Pre-Function Area | Break | |
| 5:30 pm - 8:15 pm | Grand Ballroom | Networking Cocktail & Dinner | |
| Signoff | |||
| Wednesday, July 12, 2017 | |||
| 10:30 am - 11:30 am | Jamavar | The Next Generation of HyperScale [More Info] Sharath Narayana, Synopsys | |
| 11:30 am - 12:00 pm | Jamavar | Signoff Timing Closure with Physical Aware Clock ECO Flow [More Info] Kalyan Kumar O, Qualcomm Nitin Gupta, Qualcomm Raghav Gupta, Qualcomm Arimilli Rajesh, Qualcomm | |
| 12:00 pm - 12:30 pm | Jamavar | Automated Clock Mesh Analysis Flow for Faster Turnaround [More Info] | |
| 1:30 pm - 2:00 pm | Jamavar | Evaluation of Physically Aware PT ECO Flow for Complex Multi Million Instance and Multi Voltage Designs [More Info] Navaneeth Krishnan M, NVIDIA Ramesh Bathina, NVIDIA Pradeep C R, Synopsys | |
| 2:00 pm - 2:30 pm | Jamavar | SSD SOC 16FF MV Clock Balancing Methodology via PrimeTime and Handling Low Power Complexities [More Info] Ganesh Selvaraj, Broadcom Naresh Nadipilli, Broadcom Pranjal Tiwari, Broadcom | |
| 2:30 pm - 3:15 pm | Jamavar | StarRC Update – 7nm Accuracy and Performance [More Info] Anand Veerasangaiah, Synopsys | |
| 3:30 pm - 4:00 pm | Jamavar | Effective Hierarchical Timing Closure Methodology using PrimeTime Context [More Info] Erik Gonzalez, AMD Raghu Pattipati, AMD Satyanarayana Medarametla, AMD Vidhu Joshi, AMD | |
| 4:00 pm - 4:30 pm | Jamavar | Using PrimeTime Parametric OCV Analysis Approach for 28nm FDSOI Design Signoff [More Info] Anil Yadav, STMicroelectronics Ayan Ray, STMicroelectronics Rahul Kheterpal, STMicroelectronics | |
| Systems & IP | |||
| Wednesday, July 12, 2017 | |||
| 1:30 pm - 2:00 pm | Turret Boardroom | SMS - A STAR for Effective Memory Repair Solution [More Info] Bharat Londhe, Seagate Jay Shah, Seagate Pankaj Sharma, Seagate | |
| 2:00 pm - 2:30 pm | Turret Boardroom | Optimizing SoC Integration of Synopsys DWC ADC for an Ultra-Low Power Solution [More Info] Charul Agrawal, Analog Devices Prakash Kuve, Analog Devices | |
| 2:30 pm - 3:15 pm | Turret Boardroom | Accelerating Typical Image Processing Applications using ARC EM Processors [More Info] Abhishek Bit, Synopsys | |
| 3:30 pm - 4:00 pm | Turret Boardroom | Tegra to Tegra Communication using VDK MultiSim [More Info] Praveen Wadikar, NVIDIA | |
| 4:00 pm - 4:30 pm | Turret Boardroom | Generating Statistically Accurate GFRBM Traffic Under System Load Conditions [More Info] Abinash, NXP Baljinder Sood, NXP Meenakshi Chawla, NXP Pushkar Sareen, NXP | |
| 4:30 pm - 5:00 pm | Turret Boardroom | Enabling Fault Injection in Automotive VP using Simulation Probe [More Info] Aditya Raghunath, Infineon Technologies Dineshkumar Selvaraj, Infineon Technologies Kamalakar Rachakonda, Infineon Technologies Sandeep Puttapa, Infineon Technologies | |
| Test | |||
| Wednesday, July 12, 2017 | |||
| 10:30 am - 11:00 am | Turret Boardroom | SpyGlass® DFT ADV: High Testability, SoC Connectivity, Functional Safety and Reliability [More Info] Fadi Maamari, Synopsys | |
| 11:00 am - 11:30 am | Turret Boardroom | Meeting IP Level Stringent Fault Coverage Goal with Z01X [More Info] Vaibhav Marathe, Cypress | |
| 11:30 am - 12:00 pm | Turret Boardroom | DFT Implementation Technique to Limit At-Speed Switching Activity [More Info] Akhtar Tamboli, Seagate Aniruddha Bhasale, Seagate Pankaj Sharma, Seagate | |
| 12:00 pm - 12:30 pm | Turret Boardroom | A Case Study for Optimizing Compression Ratios Across Blocks to Achieve Pattern Reduction using DFTMAX Ultra [More Info] Daryl Pereira, Broadcom Jayanthi Muthu Krishnan, Broadcom Priyesh Kumar, Broadcom Sekar Manickam, Broadcom | |
| Verification | |||
| Wednesday, July 12, 2017 | |||
| 10:30 am - 11:30 am | Grand Ballroom | Increase Your Verification Productivity with VC Formal [More Info] Neelabja Dutta, Synopsys | |
| 11:30 am - 12:00 pm | Grand Ballroom | Am I Right or Am I Right: Formal Golden Specs Lead the Way to Embracing Datapath FV [More Info] | |
| 12:00 pm - 12:30 pm | Grand Ballroom | Using VC Formal to Verify Connections Generated from Connectivity Extraction Script and Generate Toggle Coverage Report [More Info] Pratyush Mahapatra, NVIDIA Akshay Bindiganavale, NVIDIA Soumit Biswas, NVIDIA Neelabja Dutta, Synopsys | |
| 1:30 pm - 2:00 pm | Grand Ballroom | Accelerating UVM-Based Functional Verification of PCI Express [More Info] Vidya Prabhu, Broadcom Priyabrata Kundu, Broadcom Sadiya Tarannum, Synopsys | |
| 2:00 pm - 2:30 pm | Grand Ballroom | The LPDDR4 VIP for Beyond Functional Verification [More Info] Manohar Vaddineni, Qualcomm Pandithurai Sangaiyah, Qualcomm Gaurav Chugh, Synopsys | |
| 2:30 pm - 3:00 pm | Grand Ballroom | DDR Subsystem Verification using Synopsys-DDR-VIP to Improve SoC/IP Quality and Productivity [More Info] Prokash Ghosh, NXP Rakesh Kumar, NXP Bhanu Prakash Ambati, Synopsys | |
| 3:30 pm - 4:00 pm | Grand Ballroom | Fault Classification for ISO 26262 using Z01X Simulator [More Info] Maheshwara Sharma, NVIDIA Rahul Jain, NVIDIA Karthik Mani, NVIDIA | |
| 4:00 pm - 4:30 pm | Grand Ballroom | Accelerated Gate Level Simulation Through Annotation of RTL Simulation States [More Info] | |
| 4:30 pm - 5:15 pm | Grand Ballroom | VCS Performance Innovations - Fine-Grained Parallelism [More Info] Vijay Kishore Nammi, Synopsys | |
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