| Academia | |||
| Thursday, July 13, 2017 | |||
| 1:30 pm - 2:30 pm | Turret Boardroom | Open HPC Systems - The SHAKTI Way [More Info] Professor V Kamakoti, Department of Computer Science and Engineering, IIT, Madras | |
| 2:30 pm - 3:30 pm | Turret Boardroom | Reconfigurable Many-Core Architecture for Massively Parallel, High Performance Embedded SoCs [More Info] Professor S K Nandy, Department of Computational and Data Sciences, IISc, Bangalore | |
| 3:45 pm - 4:30 pm | Turret Boardroom | CMOS Manufacturing in India: Opportunities and Challenges [More Info] H S Jatana, Group Head – Process & Design Group, Semi-Conductor Laboratory, Department of Space | |
| 4:30 pm - 5:15 pm | Turret Boardroom | High Performance Embedded Computing – A Hardware Landscape [More Info] Dr. Venu Kandadai, Co-founder and CEO, Manjeera Digital Systems Pvt. Ltd. | |
| AMS | |||
| Thursday, July 13, 2017 | |||
| 10:45 am - 11:45 am | Jamavar | Using Custom Compiler’s Visually-Assisted Automation for Analog Layout [More Info] Rajagopal Sundararaman, Synopsys RakeshShenoy Panemangalore, Synopsys | |
| 11:45 am - 12:15 pm | Jamavar | Synopsys SAE Based Integrated Functional Reliability Testing [More Info] Sajal Mittal, Samsung Sandeep BV, Samsung Shyam Agarwal, Samsung Utkarsh Garg, Samsung | |
| 12:15 pm - 12:45 pm | Jamavar | Productivity Gain with Novel Placement and Smart Editing Features While Making Layouts using Custom Compiler [More Info] Atul Bhargava, STMicroelectronics Francois Lemery, STMicroelectronics Radhika Gupta, STMicroelectronics Vikas Chelani, STMicroelectronics | |
| 1:30 pm - 2:30 pm | Jamavar | Self-Heat Aware Electro-Migration (EM) Simulation and Analysis with CustomSim for FinFET Devices and Smaller [More Info] Vivek Sharma, Synopsys | |
| 2:30 pm - 3:00 pm | Jamavar | Gaining Speed While Maintaining Accuracy for Transient Temperature Sweep and Monte Carlo Simulations with CustomSim [More Info] Ankit Gupta, STMicroelectronics Nitin Gupta, STMicroelectronics Rakesh Shenoy, Synopsys | |
| 3:00 pm - 3:30 pm | Jamavar | Memory Characterization Turnaround Time Improvement using Innovative Techniques and CustomSim In-Built Post Processing Utilities [More Info] Nitin Gupta, Qualcomm Raj Sundararaman, Synopsys | |
| 3:45 pm - 4:15 pm | Jamavar | Challenges in Customized Characterization of Standard Cells [More Info] Anirban Bhattacharjee, Samsung Digambar Gangaram Devalatkar, Samsung Rajeela Deshpande, Samsung | |
| 4:15 pm - 4:45 pm | Jamavar | Liberty and IBIS Characterization Methodology at Advanced Nodes [More Info] | |
| FPGA | |||
| Thursday, July 13, 2017 | |||
| 10:45 am - 11:30 am | Turret Boardroom | Prototyping ARM® Based Designs with HAPS® [More Info] Pradeep Kumar MP, Synopsys | |
| 11:30 am - 12:15 pm | Turret Boardroom | Enabling Functional Safety for FPGA Based Hardware Design [More Info] Madhav Chikodikar, Synopsys | |
| General Sessions | |||
| Thursday, July 13, 2017 | |||
| 8:40 am - 9:45 am | Grand Ballroom | Welcome & Keynote [More Info] Girish Nanappa, Synopsys Vivek Sharma, STMicroelectronics | |
| 9:45 am - 10:30 am | Grand Ballroom | Enabling Data-Driven Approach to Chip Design [More Info] Sashi Obilisetty, Synopsys | |
| Implementation | |||
| Thursday, July 13, 2017 | |||
| 10:45 am - 11:45 am | Grand Ballroom | Mastering the Challenges of 7nm Design for Best-in-Class QoR with IC Compiler II [More Info] Neeraj Kaul, Synopsys | |
| 11:45 am - 12:15 pm | Grand Ballroom | Establishing QOR Flow on Emerging Technology Nodes [More Info] Pramod Sripathi, Xilinx Sreenivasa Reddy Kasireddy, Xilinx Raj Sekhar Bochkar, Synopsys | |
| 12:15 pm - 12:45 pm | Grand Ballroom | Improving Design QoR with Advanced Techniques [More Info] Anshuman Anand, Infineon Somshekhar Arakeri, Infineon Srikanth Gourineni, Infineon | |
| 1:30 pm - 2:30 pm | Grand Ballroom | A “Completely Cool” Case Study – Synopsys Low Power Front-End Implementation [More Info] Mahesh Narayan, Synopsys Prasan Shanbhag, Synopsys | |
| 2:30 pm - 3:00 pm | Grand Ballroom | Accelerating Advanced Low Power Test Design Flow using UPF2.0 [More Info] Kamlesh Bhesaniya, Broadcom Omar Sharif Cherukur, Broadcom Suresh Kumar, Broadcom Mahesh Narayan, Synopsys | |
| 3:00 pm - 3:30 pm | Grand Ballroom | Case Study of Complex Full Chip Low Power Implementation in 16nm Node [More Info] Aman Jain, Seagate Pritesh Pawaskar, Seagate Jay Shah, Seagate Mahesh Narayan, Synopsys | |
| 3:45 pm - 4:15 pm | Grand Ballroom | A Re-Producible Memory BIST Physical Design and Automation Methodology using Traditional Place and Route, STA, ETM Extraction Engines [More Info] Nitin Abhishek, Broadcom Mayank Dadheech, Broadcom Bhuvan Plaha, Broadcom | |
| 4:15 pm - 5:00 pm | Grand Ballroom | Boosting Power, Performance and Area of your Design using IC Compiler II [More Info] Swanand Rama Krishna Palanki, Synopsys | |
| Networking Opportunities | |||
| Thursday, July 13, 2017 | |||
| 7:30 am - 8:30 am | Lobby Garden | Registration and Breakfast | |
| 10:30 am - 10:45 am | Pre-Function Area | Break | |
| 12:45 pm - 1:30 pm | Pre-Function Area | Networking Lunch | |
| 3:30 pm - 3:45 pm | Pre-Function Area | Break | |
| 5:15 pm - 5:45 pm | Grand Ballroom | Best Paper Award | |
| Verification | |||
| Thursday, July 13, 2017 | |||
| 10:45 am - 11:15 am | Royal Ballroom | Early Pre-Silicon Power-Profile Combining Correlation and Replay Engines with an Estimation Tool Suite [More Info] | |
| 11:15 am - 11:45 am | Royal Ballroom | Simulation Debug and Bring-up Productivity Enhancement using VCS Save/Restore Concept in Hybrid SoC Verification Environment [More Info] Suresh Kamasamudram, AMD Sagar Kankanala, AMD | |
| 11:45 am - 12:45 pm | Royal Ballroom | A “Completely Cool” Case Study – Synopsys Low Power Front-End Verification [More Info] Harsha Vardhan, Synopsys | |
| 1:30 pm - 2:30 pm | Royal Ballroom | Introduction to SpyGlass Lint Turbo for 3X Violation Reduction to Accelerate RTL Design Closure [More Info] Ravindra Nibandhe, Synopsys Prashanth Shetty, Synopsys | |
| 2:30 pm - 3:00 pm | Royal Ballroom | Clock and Reset Domain Crossing Verification of a Low-power Processor Complex [More Info] Francis Chockalingam, Broadcom Viral Gorasia, Broadcom | |
| 3:00 pm - 3:30 pm | Royal Ballroom | Novel Approach in Differential CDC Analysis of Parameterized IP [More Info] Anubhav Arora, STMicroelectronics Ashish Soni, STMicroelectronics Navneet Kumar Chaurasia, Synopsys Navin Garg, Synopsys | |
| 3:45 pm - 4:15 pm | Royal Ballroom | An Effective Approach for Lint Verification Analysis [More Info] Jeyakumar Ananthappan, Qualcomm Arindam Biswas, Qualcomm | |
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