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3DIC | Artificial Intelligence | ||
Automotive | Cloud | ||
Custom Implementation & AMS | Digital Implementation - Physical | ||
Digital Implementation - RTL | General Sessions | ||
IP | Low Power Community | ||
Networking Opportunities | Signoff & Characterization I | ||
Signoff & Characterization II | Test | ||
User Content Reviewed by the Technical Committee | Verification Continuum I | ||
Verification Continuum II |
March 18, 2020 | |||||
9:00 am - 10:30 am | Santa Clara Convention Center | Keynote - Aart de Geus [More Info] Speaker: Dr. Aart de Geus, Chairman & co-CEO, Synopsys | |||
11:00 am - 11:45 am | Santa Clara Convention Center | Best in Class Emulation Debug Flow for Large Graphic Designs [More Info] Speaker: Ameya Rane, Intel | |||
11:00 am - 11:45 am | Santa Clara Convention Center | Introducing PrimeECO Signoff-driven Design Closure System [More Info] Speaker: Vivek Ghante, Product Application Engineer, Synopsys | |||
11:00 am - 11:45 am | Santa Clara Convention Center | Keynote: Using Machine Learning and AI to Reduce Power [More Info] Speaker: Dr. Kaushik Roy, Purdue University | |||
11:00 am - 11:45 am | Santa Clara Convention Center | Managing Variability in Memory Designs using HSPICE and CustomSim [More Info] Speaker: Ashish Kumar, Sr. Manager, STMicroelectronics | |||
11:00 am - 11:45 am | Santa Clara Convention Center | Performance and Coverage Optimizations for the DFT Simulation Flow [More Info] Speaker: Jerry Fremaint, Staff Engineer, Broadcom Speaker: Saket Goyal, Principal Engineer, Broadcom | |||
11:00 am - 12:00 pm | Santa Clara Convention Center | NXP and Synopsys Presents Efficient FuSa Implementation for Automotive Designs [More Info] Speaker: Thomas Koch, NXP Speaker: Mary Ann White, Synopsys | |||
11:00 am - 12:30 pm | Santa Clara Convention Center | Digital Implementation: Fusion Compiler RTL-to-GDSII Panel [More Info] Panelist: Mahesh Harinath, Senior Hardware Engineer, Microsoft Moderator: Mark Richards, Synopsys Panelist: Damien Riquet, STMicroelectronics Panelist: Tom Quan, TSMC Panelist: Rajit Seahra, AMD | |||
11:00 am - 12:30 pm | Santa Clara Convention Center | Exploring Cloud Native EDA Workflows with Verification, Characterization, Signoff [More Info] Speaker: Nanda Gopal, Synopsys Speaker: Melvin Cardozo, Synopsys Speaker: Steve Hollands, Synopsys Speaker: Ramki Balasubramanian, Synopsys | |||
11:45 am - 12:30 pm | No location | Advanced Verification Technologies for Stimulus Generation and Coverage [More Info] Speaker: Badri Gopalan, Synopsys Speaker: Bernie DeLay, Synopsys | |||
11:45 am - 12:30 pm | Santa Clara Convention Center | PGSTA Flow - PG Based Timing Closure on Low Power SSD SoC [More Info] Speaker: Ganesh Selvaraj, Principal ASIC R&D Engineer, Broadcom | |||
11:45 am - 12:30 pm | Santa Clara Convention Center | Shift-left Software Development and Validation for AI SoCs using Synopsys Hybrid Flow [More Info] Speaker: Gaurava Sharda, Synopsys | |||
11:45 am - 12:30 pm | Santa Clara Convention Center | Witnessing Behaviors Beyond the Known Boundaries with Emulation Based Power Analysis [More Info] Speaker: Satya Ayyagari, Intel | |||
11:45 am - 12:30 pm | Santa Clara Convention Center | Yield Analysis with HSPICE-AVA High Sigma Monte Carlo (HSMC) [More Info] Speaker: Oshin Jakhete, Design Enablement Engineer, Globalfoundries | |||
12:00 pm - 12:30 pm | Santa Clara Convention Center | Memory Test & Repair and Hierarchical Test Targeting Automotive SoCs [More Info] Speaker: Yervant Zorian, Synopsys | |||
12:30 pm - 2:00 pm | Santa Clara Convention Center | Lunch 'N' Learn - Achieving Predictable RTL Closure With Synopsys [More Info] | |||
12:30 pm - 2:00 pm | Santa Clara Convention Center | Lunch 'N' Learn - Industry Leaders Verify with Synopsys [More Info] Kiran Vittal, Product Marketing Director, Synopsys | |||
12:30 pm - 2:00 pm | Santa Clara Convention Center | Networking Lunch [More Info] | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | Best Practices in FCT with Mixed PnR and Custom Designs to Avoid Escapes [More Info] Speaker: Siva Prasad Reddy Samsani, Sr.Staff Design Engineer, Xilinx Speaker: Fu-Hing Ho, Xilinx | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | Increasing Emulation Efficiency for Networking SoCs using Virtual Testers [More Info] Speaker: Shenoy Mathew, Synopsys | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | Innovative Design-For-Test Methodology for AI & Automotive SoCs [More Info] Speaker: Yehonatan Abotbol, DFT Lead, Mobileye an Intel Company | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | Low Power Architectures and Deploying Challenges [More Info] Hari Hariharan, Principal Engineer, Synaptics | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | Real Number Modeling using SV Nettypes [More Info] Speaker: Nihar Veeragandham, Senior Design Engineer, Micron | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | Variability Analysis of Sensitive CMOS Circuits using HSPICE High Sigma Monte Carlo Analysis [More Info] Speaker: Raed Sabbah, Senior Staff Engineer, Micron | |||
2:00 pm - 3:30 pm | Santa Clara Convention Center | A Collaborative Method to Address 3DIC Design Complexities [More Info] Speaker: Youngsoo Lee, Synopsys | |||
2:00 pm - 3:30 pm | Santa Clara Convention Center | Case Studies: Semiconductor Design Flow with Synopsys EDA Tools on the Cloud [More Info] | |||
2:00 pm - 3:30 pm | Santa Clara Convention Center | Synopsys’ Fusion Compiler for Arm® Processor Cores in Advanced-Foundry Processes [More Info] Speaker: Lakshmi Jain, Sr. Product Marketing Manager, Arm Speaker: Dale Lomelino, Sr. Staff Applications Engineer , Synopsys | |||
2:45 pm - 3:30 pm | Santa Clara Convention Center | C-solver Based Random Stimulus Generation for Functional Design Verification [More Info] Speaker: Mukhdeep Singh Benipal, Asic Verification Engineer, Nvidia | |||
2:45 pm - 3:30 pm | Santa Clara Convention Center | Comparative Analysis of Flip-flop Architectures and Determining their Energy Efficient Usage Methodology with AMS Verification and Sign-off in FINFET Technology Nodes [More Info] Speaker: Deepon Saha, Member of Technical Staff, AMD | |||
2:45 pm - 3:30 pm | Santa Clara Convention Center | Latch Timing - Demystified [More Info] Speaker: Zafar Hasan, Principal Engineer, Nvidia | |||
2:45 pm - 3:30 pm | No location | Shifting Left with Virtualizer: End-to-end Virtual Prototype for Automotive Ethernet Switch [More Info] Speaker: Wei Liu, Marvell | |||
2:45 pm - 3:30 pm | Santa Clara Convention Center | Team Geriatric Guys with Gates Participates in the VDF Speed Competition: It’s All About Speed and Power [More Info] Speaker: Steve Golson, Consultant, Trilobyte Systems Speaker: Kurt Baty, Consultant, WSFDB Consulting | |||
3:45 pm - 4:15 pm | Santa Clara Convention Center | Getting Signoff Right for Low Power GALS Clocking [More Info] | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | Accelerating Analog and RF Simulation Flow with the Synopsys Custom Design Platform [More Info] Speaker: Preeti Jain, Synopsys Speaker: Khaled Nikro, R&D Engineer, Synopsys | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | Automated Interconnect Planning & Implementation for Networking Designs using IC Compiler II [More Info] Speaker: Balakrishna Janapati, Physical Design Engineer, Juniper | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | Case Study of Fault Injection Campaign on an DCLS ASIL-D ARC Processor using Z01X [More Info] Speaker: Shradha Borkute, Synopsys Speaker: Shivakumar Chonnad, Senior Staff Enginner, Synopsys Speaker: Jaimin Desai, Synopsys | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | HAPS Unified Compile Flow [More Info] Speaker: Amir Salehi, Synopsys Speaker: Sivaramalingam Palaniappan, Synopsys | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | Panel: ZeBu [More Info] | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | Preventing and Reducing Dynamic IR Drop Issues using Redhawk-SC Fusion [More Info] Speaker: Swati Jindal, Senior Hardware Designer, Microsoft Speaker: Mahesh Harinath, Senior Hardware Engineer, Microsoft | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | STA Productivity Improvement and Large Design Handling [More Info] Speaker: Kenneth Hung, Applications Engineer, Staff, Synopsys | |||
3:45 pm - 5:15 pm | Santa Clara Convention Center | VCS Performance and Productivity Updates [More Info] Speaker: Amir Salehi, Synopsys Speaker: Rohit Narkar, Synopsys Speaker: Mansour Amirfathi, Synopsys | |||
4:15 pm - 4:45 pm | Santa Clara Convention Center | Bridging the Gap Between Power Sign-off and Validation [More Info] Speaker: Anand Iyer, Senior Design Engineer, Microsoft | |||
4:30 pm - 5:15 pm | Santa Clara Convention Center | Extraction of Digital Test Stimulus for Reuse in Analog/Mixed-Signal Testbenches [More Info] Speaker: Benjamin Sissons, Software Engineer, Intel Speaker: Krithivas Mannarkudi Ramachandran Krishnaswami, Design Automation Engineer, Intel | |||
4:30 pm - 5:15 pm | Santa Clara Convention Center | FPGA - Emulation UPF Enabled Flow for IP Development [More Info] Speaker: Manish Gajjar, Intel | |||
4:30 pm - 5:15 pm | Santa Clara Convention Center | Improving Design Yield and Robustness using PrimeYield [More Info] Speaker: Ayhan Mutlu, Synopsys | |||
4:30 pm - 5:15 pm | Santa Clara Convention Center | Methodology to Implement Supply Strap Location-Aware Low Power Designs [More Info] Speaker: Ben Mathew, Senior Staff Product Engineer, Synopsys | |||
4:30 pm - 5:15 pm | Santa Clara Convention Center | Panel: State of EDA Cloud 2020 [More Info] | |||
4:30 pm - 5:15 pm | Santa Clara Convention Center | Role of IP in Functional Safety Flows for Automotive Applications [More Info] Speaker: Shivakumar Chonnad, Senior Staff Enginner, Synopsys | |||
4:30 pm - 5:15 pm | Santa Clara Convention Center | Timing-Path-Based Feedthrough Insertion and Pin Placement [More Info] Speaker: Aamod Panvalkar, Senior Physical Design Engineer, Nvidia | |||
4:45 pm - 5:30 pm | Santa Clara Convention Center | Panel: Low Power [More Info] Panelist: Dr. Kaushik Roy, Purdue University Moderator: Renu Mehra, Synopsys | |||
5:15 pm - 7:00 pm | Santa Clara Convention Center | SNUG Pub [More Info] | |||
March 19, 2020 | |||||
9:00 am - 10:30 am | Santa Clara Convention Center | Keynote - Jeff Dean [More Info] Speaker: Jeff Dean, Senior Fellow and SVP of Google Research and Health, Google | |||
11:00 am - 11:30 am | Santa Clara Convention Center | StarRC Digital & Custom Update [More Info] Speaker: Krishna Kumar Sundaresan, Synopsys | |||
11:00 am - 11:45 am | Santa Clara Convention Center | "Shift Left' Low Power Static Verification using Design Independent UPF Checking and Machine Learning Based Root Cause Analysis [More Info] Speaker: Weih Liou, Broadcom | |||
11:00 am - 11:45 am | Santa Clara Convention Center | Achieving the Best Total Power Using Fusion Compiler [More Info] Speaker: Alak Ghosh, Senior Staff Applications Engineer, Synopsys | |||
11:00 am - 11:45 am | Santa Clara Convention Center | Die-to-Die PHY IP with SerDes or Parallel Interfaces - You Choose! [More Info] Speaker: Manmeet Walia, Sr. Product Marketing Manager, Synopsys | |||
11:00 am - 11:45 am | Santa Clara Convention Center | Formality 2019.12 Updates [More Info] Speaker: Padmashree Takkars, Synopsys | |||
11:00 am - 11:45 am | Santa Clara Convention Center | Ingredients for Creating Success Story in RTL to RTL Equivalence Verification [More Info] Speaker: Arun Singh, GPU Formal Verification Engineer, Samsung | |||
11:00 am - 11:45 am | Santa Clara Convention Center | Leveraging Process-Specific Quick Start Kits to Reduce Mixed-signal IP Design TAT [More Info] Speaker: Neel Gopalan, Principal Engineer, Synopsys | |||
11:00 am - 11:45 am | Santa Clara Convention Center | Test Shifts Left: DFT RTL for Earlier Verification [More Info] Speaker: Fadi Maamari, Synopsys | |||
11:00 am - 11:45 am | Santa Clara Convention Center | The Road to Artificial Intelligence in Chip Design [More Info] Speaker: Jimmy Kim, Engineer, Samsung Speaker: Stelios Diamantidis, Synopsys Speaker: Joe Walston, Synopsys | |||
11:00 am - 12:30 pm | Santa Clara Convention Center | Accelerating Physical Verification Closure using IC Validator [More Info] Speaker: Troy Tamas, Senior Photonics Design Automation Engineer, Rockley Photonics Speaker: Yongjin Kwon, LG Electronics Speaker: Anil Karanam, Group Dir, R&D, Synopsys | |||
11:30 am - 12:00 pm | Santa Clara Convention Center | Using Synopsys QuickCap for Reference Flow Development to Design ARM Physical IP [More Info] Speaker: Tom Mahatdejkul, Arm | |||
11:45 am - 12:30 pm | Santa Clara Convention Center | Addressing Tomorrow's Static Verification Challenges [More Info] Speaker: Namit Gupta, Synopsys | |||
11:45 am - 12:30 pm | Santa Clara Convention Center | Advanced Data Management Techniques with Synopsys Custom Compiler and IC Manage GDP [More Info] Speaker: Alex Tumanov, Director of Applications Engineering, IC Manage | |||
11:45 am - 12:30 pm | Santa Clara Convention Center | Automotive Safety and Quality Drive Test Innovation [More Info] Speaker: Surya Duggirala, Synopsys | |||
11:45 am - 12:30 pm | Santa Clara Convention Center | Formal Verification of Design with SEU Mitigation Techniques by State Element Modeling [More Info] Speaker: Tony Cai, Verification Engineer, Xilinx | |||
11:45 am - 12:30 pm | Santa Clara Convention Center | Formality Automated ECO Technology Overview [More Info] Speaker: Padmashree Takkars, Synopsys | |||
11:45 am - 12:30 pm | Santa Clara Convention Center | Hardware Implementation of Convolutional Neural Network Layers [More Info] Speaker: Satheesh Appukuttan, Broadcom Speaker: Tara Keigharn, Senior Systems Engineer II, Raytheon | |||
11:45 am - 12:30 pm | Santa Clara Convention Center | How to Select the Right DRAM for your SoC: DDR5, LPDDR5, HBM2E, or GDDR6 [More Info] Speaker: Brett Murdock, Sr. Product Marketing Manager, Synopsys Speaker: Vadhi Sankaranarayanan, Synopsys | |||
11:45 am - 12:30 pm | Santa Clara Convention Center | Seamless Transition to New Features in RTL-to-GDSII Implementation Product for a Large SoC Design [More Info] Speaker: Jina Kim, Senior Staff Engineer, Intel | |||
12:00 pm - 12:30 pm | Santa Clara Convention Center | Accurate Clock Network Analysis using StarRC [More Info] Speaker: Tony Todesco, AMD Speaker: Esha Dubey, AMD | |||
12:30 pm - 2:00 pm | Santa Clara Convention Center | Lunch 'N' Learn - Synopsys Custom Design Platform: Accelerating Robust Custom Design [More Info] | |||
12:30 pm - 2:00 pm | Santa Clara Convention Center | Lunch 'N' Learn - Synopsys Signoff Platform: Innovations in Design Sign-off [More Info] | |||
12:30 pm - 2:00 pm | Santa Clara Convention Center | Networking Lunch [More Info] | |||
2:00 pm - 2:30 pm | Santa Clara Convention Center | Improving Scan Compression ATPG Results by Analyzing and Reducing the Effects of Decompressor Dependencies [More Info] Speaker: Richard Illman, Member of Technical Staff, Dialog Semiconductor | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | 2019.12 IC Compiler II Update [More Info] Speaker: Frank De Meersman, Synopsys | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | Detecting and Preventing Parasitic Double Counting Due to LVS Layer Formation in the StarRC Flow [More Info] Speaker: Arnold Baizley, LVS Technical Lead, Globalfoundries | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | ECO Synthesis Gate Level Netlist of FSM with Formality [More Info] Speaker: Sathappan Palaniappan, Principal Engineer, Broadcom | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | Formally Sign-off Floating Point Datapath with DPV [More Info] Speaker: Lijun Li, Intel | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | Integrating Real Software Driver Traces for Pre-Silicon UVM Simulation Stimulus for Intel Accelerator Prototyping [More Info] Speaker: Anupama Toshniwal, SoC Design Engineer, Intel | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | IR Drop Aware Static Timing Analysis [More Info] Speaker: Kapil Bhargava, Engineering Manager, Intel | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | Machine Learning Driven Digital Implementation Technologies Overview [More Info] Speaker: Geetha Rangarajan, Synopsys Speaker: Vishal Khandelwal, Synopsys | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | Pitfalls of Power Estimation for AI & Vision SoCs, and How to Avoid Them [More Info] Speaker: Derya Eker, Synopsys | |||
2:00 pm - 2:45 pm | Santa Clara Convention Center | Synopsys TestMAX CustomFault - Redefining Analog Fault Simulation [More Info] Speaker: Anand Thiruvengadam, Senior Manager, Product Marketing, Synopsys | |||
2:30 pm - 3:00 pm | Santa Clara Convention Center | Samsung Foundry Presents New Technology for Faster and Accurate Diagnostics and Yield Analysis [More Info] Speaker: DK Han, Samsung | |||
2:45 pm - 3:10 pm | Santa Clara Convention Center | Accelerating Design Closure using Machine Learning Enabled Routability Prediction in IC Compiler II [More Info] Speaker: Kwangok Jeong, Samsung | |||
2:45 pm - 3:30 pm | Santa Clara Convention Center | Analog Fault Simulation in ISO 26262 Applications [More Info] Speaker: Erich Gottlieb, Micronas Speaker: Gernot Koch, CAD Manager, Micronas | |||
2:45 pm - 3:30 pm | Santa Clara Convention Center | Best Practices in Building Hierarchical Clock Mesh and Automation Flow [More Info] Speaker: Jun Seomun, Principal Engineer, Samsung | |||
2:45 pm - 3:30 pm | Santa Clara Convention Center | Finding the Right Cycles: Efficient Peak and Average Power Analysis, Accurate Power Estimation and IR Profiling for Next Generation Synaptics IoT SoC [More Info] Speaker: Sudhir Chandel, Synaptics | |||
2:45 pm - 3:30 pm | Santa Clara Convention Center | Improve Verification Efficiency and Design Quality with Formal Tools [More Info] Speaker: Anna Chang, Design and Verification Engineer, Broadcom | |||
2:45 pm - 3:30 pm | Santa Clara Convention Center | Improving Early Power Estimation Accuracy When using Fusion Compiler [More Info] Speaker: Swati Jindal, Senior Hardware Designer, Microsoft Speaker: Anshul Bansal, Hardware Engineer, Microsoft Speaker: Anand Iyer, Senior Design Engineer, Microsoft | |||
2:45 pm - 3:30 pm | Santa Clara Convention Center | Maxim's Power Management ICs Powered by Synopsys DesignWare Non-Volatile Memory (NVM) IP [More Info] Speaker: Adam Brand, Maxim | |||
2:45 pm - 3:30 pm | Santa Clara Convention Center | NanoTime Memory for ROMs [More Info] Speaker: Sudha Vasu, Nvidia | |||
2:45 pm - 3:30 pm | Santa Clara Convention Center | Shift-left: Efficient Pre-silicon SoC Validation using FSDB Programming Interface [More Info] Speaker: Vaibhav Gupta, Graphics Hardware Engineer, Intel | |||
3:00 pm - 3:30 pm | Santa Clara Convention Center | High-Speed Scan for ATE and SLT Live Demo! [More Info] Speaker: Brian Archer, Synopsys | |||
3:10 pm - 3:30 pm | Santa Clara Convention Center | Machine Learning Driven Timing Prediction and Optimization in IC Compiler II [More Info] Speaker: Jimmy Kim, Engineer, Samsung | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | Advantages of Layered UVM Agents and Environments [More Info] Speaker: Nipun Bhatt, Infinera Speaker: Yanping Zhao, Infinera | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | AI Inference Modeling Methodology [More Info] Speaker: Priya Joshi, Intel | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | ATPG and Diagnostics Advance with Machine Learning [More Info] Speaker: Girish Patankar, Synopsys Speaker: Brian Archer, Synopsys | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | Early Glitch Power Analysis using PrimePower Activity Delay Shifting [More Info] Speaker: Vidhyadharan Jayapal, Synopsys | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | High Sigma LVF Constraint Characterization with Fast Monte Carlo [More Info] Speaker: Bhargavi Pothula, Software Engineer, Intel | |||
3:45 pm - 4:30 pm | Santa Clara Convention Center | Motivation for Physical CDC Verification [More Info] Speaker: Mark Kelley, Senior Staff Engineer, Xilinx | |||
3:45 pm - 4:45 pm | Santa Clara Convention Center | 2019.12 Design Compiler NXT Tutorial [More Info] Speaker: Avinash Mane, Synopsys | |||
3:45 pm - 4:45 pm | Santa Clara Convention Center | Designing for Reliability using Synopsys Custom Design Platform [More Info] Speaker: Kai Wang, Engineering Director, Synopsys | |||
3:45 pm - 5:15 pm | Santa Clara Convention Center | Physical Verification Fusion using IC Validator: Technology Update [More Info] Speaker: Ed Roseboom, Sr Staff Engineer, Synopsys | |||
4:30 pm - 5:15 pm | Santa Clara Convention Center | Accelerating Formal Qualification for Multiple HW Configurations with Certitude [More Info] Speaker: Giovanni Auditore, Senior Staff Verification Engineer, STMicroelectronics | |||
4:30 pm - 5:15 pm | Santa Clara Convention Center | Automated Custom Macro Characterization using Commercially Available Standard Cell Characterization Tools [More Info] Speaker: Malisa Novakovic, Principal Member of Technical Staff, Intel | |||
4:30 pm - 5:15 pm | Santa Clara Convention Center | Locate Minimum Post-silicon Test Set for Toggle Coverage using FPGA [More Info] Speaker: Jing Zhang, Intel | |||
4:30 pm - 5:15 pm | Santa Clara Convention Center | Static Analysis for Functional Safety [More Info] Speaker: Jamileh Davoudi, Sr. Staff Product Marketing Manager, Synopsys | |||
4:30 pm - 5:15 pm | Santa Clara Convention Center | System-level Power and Performance Optimization of AI SoC Architectures [More Info] Speaker: Tim Kogel, Synopsys | |||
5:15 pm - 7:00 pm | Santa Clara Convention Center | SNUG 30th Anniversary Party & Awards [More Info] |
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