| 08:00 - 09:15 | Ballroom 3 and 4 Foyer | | Registration / Networking Breakfast [More Info] |
| 09:15 - 09:35 | Ballroom 4 | | Welcome [More Info] |
| 09:35 - 10:15 | Ballroom 4 | | Keynote: High Impact Innovation [More Info]
Sassine Ghazi, Sassine Ghazi - General Manager Design Group, Corporate Staff, Synopsys
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| 10:20 - 11:00 | Ballroom 4 | | Keynote: How UX in the Era of AI Transforms the Electronics Industry [More Info]
Mario Traeber, Head of R&D SoC, Intel
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| 11:05 - 11:30 | Ballroom 3 | | My Swiss Army Knife of Static Timing Analysis [More Info] |
| 11:05 - 11:30 | Ballroom 4 | | Optimal Clock Latency Through Physical Clock Path Analysis [More Info] |
| 11:05 - 11:30 | Function Room 8 | | Register and Logic Duplicator [More Info] |
| 11:05 - 11:30 | Ballroom 1 | | Using SVA to Mitigate CDC/RDC Escapes in Silicon [More Info] |
| 11:35 - 12:15 | Ballroom 4 | | Block Level CTS Debug with IC Compiler II [More Info]
Tan Chin Eng, Synopsys
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| 11:35 - 12:15 | Ballroom 1 | | High Performance Formal Verification: A Perfect Use of Machine Learning Techniques / VC-Formal’s case study and success in collaboration with Synopsys [More Info]
Jonathan Cheah, Synopsys
Pham Van Khich, Renesas
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| 11:35 - 12:15 | Ballroom 3 | | Machine Learning Accelerated ECO and Latest Advances with PrimeTime-ADVPlus [More Info]
Vivek Ghante, Synopsys
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| 11:35 - 12:15 | Function Room 8 | | TestMAX Platform – DFT Shifts Left to Accelerate Time to Results! [More Info]
Siva Kumar Etikala, Synopsys
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| 12:15 - 13:35 | Ballroom 2 | | Networking Lunch [More Info] |
| 13:35 - 14:00 | Ballroom 1 | | Debugging Technique of the UVM Testbench using Synopsys VCS/Verdi [More Info]
Mitsuhiro Taguchi, CM Engineering Vietnam Co., Ltd
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| 13:35 - 14:00 | Function Room 8 | | Full Flow Physical Verification Productivity using IC Validator [More Info]
Jocelyn Chua, Synopsys
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| 13:35 - 14:00 | Ballroom 3 | | Leakage Power and Area Recovery on High Density Block [More Info] |
| 13:35 - 14:00 | Ballroom 4 | | Spice Versus PnR Versus Signoff Correlation During Design Planning [More Info] |
| 14:05 - 14:45 | Function Room 8 | | Analog/Custom Design Closure [More Info]
Jiang Xi, Synopsys
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| 14:05 - 14:45 | Ballroom 3 | | Design Compiler® NXT and Power Compiler - Tutorial Covering Latest Release Updates [More Info]
Loh Sek Nee, Synopsys
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| 14:05 - 14:45 | Ballroom 4 | | IC Compiler II Update [More Info]
Jason Chia Ie Chen, Synopsys
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| 14:05 - 14:45 | Ballroom 1 | | Using Simulation Acceleration to Speed Block and Platform Level IP Verification [More Info]
Sivaprasad Acharaya, Synopsys
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| 14:50 - 15:15 | Ballroom 4 | | Accelerating Faster Time to Results Through Next Generation of RTL-to-GSDII Implementation Tool [More Info] |
| 14:50 - 15:15 | Ballroom 3 | | Congestion Prevention Synthesis Flow to Address MUX Connectivity Challenge with Design Compiler [More Info]
Khai Sean Yeoh, Xilinx Asia Pacific
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| 14:50 - 15:15 | Ballroom 1 | | Gate Level Simulation Process with Synopsys FGP (Cheetah) Acceleration Engine [More Info] |
| 14:50 - 15:15 | Function Room 8 | | PrimePower: The Next Generation Power Signoff [More Info]
Teng Wei Khoon, Synopsys
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| 15:20 - 16:00 | Ballroom 4 | | Best Practices using Synopsys Fusion Technology to Achieve High-Performance, Energy Efficient Implementations of the Latest Arm® Processors in 7-Nanometer FinFET (7FF) Process Technology [More Info]
Sandeep Jain, Synopsys
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| 15:20 - 16:00 | Ballroom 1 | | Early UPF Checking and Hierarchical Low Power Static Verification [More Info]
Hoe Lay Fang, Synopsys
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| 15:20 - 16:00 | Function Room 8 | | Efficient Monte Carlo Solution Including High Sigma Designs and Update on Accelerating Simulation of High Accuracy Analog Designs [More Info]
Jiang Xi, Synopsys
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| 15:20 - 16:00 | Ballroom 3 | | StarRC Product Update and Advanced Analysis/Debugging with StarRC Parasitic Explorer [More Info]
Lee Yeong Bin, Synopsys
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| 16:00 - 16:25 | Ballroom 3 and 4 Foyer | | Tea Break [More Info] |
| 16:30 - 17:10 | Ballroom 4 | | Common Technology Session - Energy Efficient ASIC Methodology [More Info]
Godwin Maben, Synopsys
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| 17:10 - 17:30 | Ballroom 4 | | Best Paper Awards & Lucky Draw [More Info] |
