| 09:00 - 10:15 | Grand Ballroom | | Synopsys Keynote: New Technologies Driving Innovation [More Info]
Speaker: Dr. Chi-Foon Chan, President and co-Chief Executive Officer, Synopsys
|
| 10:30 - 11:00 | Turret Boardroom | | Shift Left TestMAX™ Flow and X-tolerant Logic BIST Solution for Automotive IC’s [More Info]
Thryambak Chandilya, Synopsys
|
| 10:30 - 11:30 | Royal Ballroom | | Formal Regressions Resource Hungry Waste or High Value Results [More Info]
Speaker: Nitin Ahuja, Synopsys
|
| 10:30 - 11:30 | Grand Ballroom | | Fusion Compiler: A New Era in High-performance Digital Design [More Info]
Speaker: Sanjay Bali, Synopsys
|
| 10:30 - 11:30 | Jamavar | | No Vectors? No Problem! Analyzing Power Earlier with PrimePower 2019 [More Info]
Godwin Maben, Synopsys
|
| 11:00 - 11:30 | Turret Boardroom | | Core Wrapping Challenges in Power Aware Designs [More Info] |
| 11:00 - 16:00 | Sitara Hall | | Visiting Sponsors [More Info] |
| 11:30 - 12:00 | Jamavar | | A Graph Based Modelling of Multi-Input Switching(MIS) in STA [More Info]
Speaker: Amartya Mazumdar, Nvidia
|
| 11:30 - 12:00 | Royal Ballroom | | Hybrid Technique for Reset Verification using Formal Capabilities [More Info]
Speaker: Immidisetti Krishna Priyanka, Qualcomm
|
| 11:30 - 12:00 | Grand Ballroom | | Multi-million Gate Implementation using Fusion Compiler [More Info]
Speaker: Sudhakar Alur, Qualcomm
|
| 11:30 - 12:00 | Turret Boardroom | | Novel Recipe for Transition Fault Test Time Reduction [More Info]
Speaker: Gourav Biyani, Broadcom
|
| 12:00 - 12:30 | Turret Boardroom | | Automated ECO Scan Stitching Flow in IC Compiler II [More Info]
Speaker: Fahim Aziz Mohammad, Advanced Micro Devices
|
| 12:00 - 12:30 | Royal Ballroom | | Complementing Simulation with VC Formal [More Info]
Speaker: Srinivasan Venkataramanan, Infinera
|
| 12:00 - 12:30 | Grand Ballroom | | Power Optimization for High Performance Digital Signal Processing ASICs on 7nm FF+ [More Info]
Speaker: Kashyap Kansara, Broadcom
|
| 12:00 - 12:30 | Jamavar | | PrimeTime Runtime and Memory Optimization for Signoff STA of Multi-million High Frequency Designs [More Info]
Speaker: Parth Banugaria, Qualcomm
|
| 13:30 - 14:00 | Royal Ballroom | | A Novel Approach for Verification of Data Integrity of Algorithmic Blocks using FPV [More Info]
Speaker: Aravind RK, Qualcomm
|
| 13:30 - 14:15 | Turret Boardroom | | Accelerating Design Cycles with Software Workload Models and Cycle Accurate Hardware Models A Home Gateway SoC Case Study [More Info] |
| 13:30 - 14:15 | Grand Ballroom | | Accelerating EMIR Closure with RedHawk Analysis Fusion [More Info]
Speaker: Prabin Prince, Synopsys
Speaker: Raghavendra Swami Sadhu, Samsung
|
| 13:30 - 14:15 | Jamavar | | Machine Learning Accelerated ECO and Latest Advances with PrimeTime-ADVPlus [More Info]
Speaker: Arundas Haridas, Synopsys
|
| 14:00 - 14:30 | Royal Ballroom | | Methodology for Simulating Non-determinism in Non-module Partitioned Design [More Info]
Speaker: Pavan Yakamuri, Nvidia
|
| 14:15 - 14:45 | Grand Ballroom | | Accelerating EMIR Signoff at Place and Route with RedHawk Analysis Fusion [More Info]
Speaker: Mohini Somvanshi, Seagate
|
| 14:15 - 14:45 | Jamavar | | An Efficient Approach for Early Detection and Solution of Min-max Timing Paths [More Info] |
| 14:15 - 14:45 | Turret Boardroom | | Enhanced Approach for Performance simulation in USB Subsystem [More Info]
Speaker: Thangavel Swamynathan, Qualcomm
|
| 14:30 - 15:15 | Royal Ballroom | | Functional Safety (ISO 26262) Verification for Automotive SoCs [More Info]
Speaker: Sesha Sai Kumar CV, Synopsys
|
| 14:45 - 15:15 | Turret Boardroom | | Cycle Models for Pre-SI Performance Validation [More Info]
Speaker: Jagadish Mysore, Infineon
|
| 14:45 - 15:15 | Grand Ballroom | | IC Compiler II MSCTS Solution for High Performance ASICs in 7nm Node [More Info]
Speaker: Manoj Gunnam, Broadcom
|
| 14:45 - 15:15 | Jamavar | | PrimeTime Productivity Improvement: DMSA Best Practices & IMSA Roll-Up reporting [More Info]
Speaker: Damodaran Trikkadeeri, Synopsys
|
| 15:30 - 16:00 | Royal Ballroom | | An Efficient Approach for Functional Safety Diagnostic Coverage Validation using Concurrent Fault Simulator [More Info] |
| 15:30 - 16:00 | Grand Ballroom | | The "Art" of Gauging Crosstalk Delay Accuracy and the "Science" of Taking it to Closure [More Info]
Speaker: Abhishek Sampagavi, ARM
|
| 15:30 - 16:15 | Turret Boardroom | | Enabling 400G Hyperscale Data Centers with 56G Ethernet PHY IP [More Info]
Speaker: Priyank Shukla, Synopsys
|
| 15:30 - 16:30 | Jamavar | | StarRC Product Update and Advanced Analysis/Debugging with StarRC Parasitic Explorer [More Info]
Speaker: Vidhya Prakash, Synopsys
|
| 16:00 - 16:30 | Royal Ballroom | | Verification Closure of Automotive Ethernet TSN with Synopsys VIP [More Info]
Speaker: Aditi Gupta, NVIDIA
|
| 16:00 - 16:30 | Grand Ballroom | | Faster TAT for Design Sign-off using Physical Verification Extensible Features [More Info] |
| 16:15 - 16:45 | Turret Boardroom | | Performance Modelling Methodology for Architecture Definition and Firmware Calibration [More Info] |
| 16:30 - 17:00 | Royal Ballroom | | Accelerated Functional Verification using UVM Based MIPI SPMI VIP [More Info]
Speaker: Sanjeev Kumar, Qualcomm
|
| 16:30 - 17:00 | Jamavar | | DRC Aware Routing Algorithm for Sign-off ECO fixes [More Info] |
| 16:30 - 17:30 | Grand Ballroom | | Full Flow Physical Verification Productivity using IC Validator [More Info]
Speaker: Chris Grossmann, Synopsys
|
| 16:45 - 17:15 | Turret Boardroom | | Verification Methodology and Practices for Coverage Planning and Closure in USB 3.1 Subsystem [More Info]
Speaker: Juhi Saraswat, Qualcomm
|
| 17:00 - 17:30 | Royal Ballroom | | A Split-Share-Stitch Approach for Compile Time Optimization [More Info]
Speaker: Guru Venkatesh Kethepalli, Nvidia
|
| 17:30 - 18:30 | Grand Ballroom Foyer | | Networking Over High-Tea [More Info] |
| |
| 09:00 - 10:15 | Grand Ballroom | | Industry Keynote: Challenges in Designing 5G SoCs in New Technology Nodes [More Info]
Venugopal Puvvada, Vice-President Engineering, Qualcomm
|
| 10:30 - 11:00 | Turret Boardroom | | Leveraging Synopsys Virtual Transactors for the Early Software Verification and Bring up of SoC [More Info]
Speaker: Alim Akhtar, Samsung
Speaker: Manikandan P V, Samsung
|
| 10:30 - 11:30 | Jamavar | | Accelerating Simulation of High Accuracy Analog Designs with FineSim® SPICE [More Info]
Speaker: Ravi Tembhekar, VP, Applications Engineering, Synopsys
|
| 10:30 - 11:30 | Grand Ballroom | | Best Practices using Synopsys Fusion Technology to Achieve High-performance, Energy Efficient Implementations of the Latest Arm Processors in 7-nanometer FinFET (7FF) Process Technology [More Info]
Speaker: Anu Uppaluri, Synopsys
Speaker: Deep Kanwar Singh Bhullar, ARM
|
| 10:30 - 11:30 | Royal Ballroom | | Fast Static Report(s) Sign-off using ML Clustering Based Root Cause Analysis [More Info]
Speaker: Harsha Vardhan Dasagrandhi, Synopsys
|
| 10:30 - 12:30 | Diya | | Panel Discussion [More Info] |
| 11:00 - 11:30 | Turret Boardroom | | Ideas for Better Prototyping using HAPS [More Info]
Speaker: Ramesh R Nair, Western Digital
|
| 11:30 - 12:00 | Grand Ballroom | | Accelerated Design Convergence with ECO Fusion Flow [More Info]
Speaker: Vaishnavi Chauhan, Qualcomm
|
| 11:30 - 12:00 | Jamavar | | Need for Iterative MOS Reliability Analysis for High Voltage Level Shifter of IO Buffers [More Info]
Speaker: Sasi Rama Subrahmanyam Lanka, Xilinx
|
| 11:30 - 12:00 | Royal Ballroom | | Netlist CDC Signoff - Challenges and Solution [More Info]
Speaker: Pratik Suthar, Nvidia
|
| 11:30 - 12:00 | Turret Boardroom | | Simulation, Emulation and Co-Emulation on Arm Graphics Designs [More Info]
Speaker: Pragati Mishra, ARM
|
| 12:00 - 12:30 | Turret Boardroom | | Accelerating Low Power Chip Tape-out using Synopsys HAPS FPGA Prototyping Platform and Protocompiler UPF flow [More Info]
Speaker: Vinayak Koparkar, Broadcom
Speaker: Abhijith Prabhavathy Sudhakaran, Broadcom
|
| 12:00 - 12:30 | Grand Ballroom | | Achieving High Metal Density and Low Latency Bus Implementation on 17 Metal Stack 7ff Technology [More Info]
Speaker: Jasmeet Singh, Xilinx
|
| 12:00 - 12:30 | Royal Ballroom | | Efficient Way to Ensure Coverage of Voltage Domain Crossing Components using VC Static [More Info]
Speaker: Vidhu Joshi, Advanced Micro Devices
|
| 12:00 - 12:30 | Jamavar | | Optimizing Design and Simulation Run Times of Custom Analog Mixed-Signal Circuits using Synopsys' Simulation and Analog Environment (SAE) [More Info]
Speaker: Pramod Baliga, AMD
|
| 13:30 - 13:45 | Turret Boardroom | | Welcome Note [More Info]
Speaker: Raja Subramaniam, Country Director, Synopsys
|
| 13:30 - 14:00 | Jamavar | | Accurate Timing Signoff using Enhanced LVF Modeling [More Info]
Speaker: Geethesh Pillari, Qualcomm
|
| 13:30 - 14:00 | Royal Ballroom | | Power Estimation using Spyglass Power [More Info]
Speaker: Srinath Pai, Juniper Networks
|
| 13:30 - 14:30 | Kamal | | Billion-Cycle Power Estimation using Fast Emulation [More Info]
Speaker: Nithya Raghavan, Dir, Application Engineer, Synopsys
|
| 13:30 - 14:30 | Grand Ballroom | | Design Compiler NXT - Introduction, Migration and Features [More Info]
Speaker: Philip Issac, Sr. Manager Application Engineer , Synopsys
|
| 13:45 - 14:30 | Turret Boardroom | | A Gentle Introduction to Generative Adversarial Networks with some Practical Applications [More Info]
Speaker: Professor Ravi Kothari, Department of Computer Science - Ashoka University
|
| 14:00 - 14:30 | Royal Ballroom | | Accurate and Reliable CDC Verification Closure [More Info]
Speaker: Ramanada Reddy Bhimireddy, Qualcomm
|
| 14:00 - 14:30 | Jamavar | | Voltage Marker Insertion and Validation Technique to Mitigate High Voltage DRC Issues using Synopsys CustomSim Circuit Check [More Info]
Speaker: Aniket Waghide, AMD
|
| 14:30 - 15:00 | Kamal | | Accelerating Volume Validation on FPGA Platform [More Info] |
| 14:30 - 15:00 | Grand Ballroom | | Parallel Per-Critical-Clock (PPCC) Logic Synthesis and Netlist Fusion for Best PPA and Convergence [More Info]
Speaker: Sandip Sar, Qualcomm
|
| 14:30 - 15:00 | Royal Ballroom | | Simple Solutions to Solve Complex RDC Violations [More Info] |
| 14:30 - 15:00 | Jamavar | | Tackling EM Effects During Layout Development using Custom Compiler [More Info]
Speaker: Tushar Sharma, STMicroelectronics
|
| 14:30 - 15:30 | Turret Boardroom | | Shakti Roadmap for Edge Intelligence [More Info]
Speaker: Professor Kamakoti, Department of Electrical Engineering, IIT - Chennai
|
| 15:00 - 15:30 | Grand Ballroom | | Case Study of Full-Chip Flat Formality with Parameterized System Verilog [More Info]
Speaker: Narayan Patil, Seagate
|
| 15:00 - 15:30 | Royal Ballroom | | Mixed Methodology : A Smart Methodology to Migrate from Traditional Low Power Methodology [More Info] |
| 15:00 - 15:30 | Kamal | | Pushing the FPGA Prototypes Performance Higher - 50+ MHz on HAPS [More Info]
Speaker: Ramanan Sanjeevi Krishnan, NVIDIA
|
| 15:45 - 16:15 | Kamal | | Debugging Indeterminism, Deterministically using Emulator DPI and Snapshot Mechanism [More Info] |
| 15:45 - 16:15 | Grand Ballroom | | Hierarchical Implementation for SOC using Block Abstracted and Timing Extracted Models for a Complex Multi-million Design [More Info] |
| 15:45 - 16:15 | Jamavar | | Validation of Power-Down Modes Functionality in Embedded Memory IP Using ESP-CV [More Info] |
| 15:45 - 16:30 | Turret Boardroom | | Resource Constrained Machine Learning [More Info]
Professor Santanu Chaudhury, Department of Electrical Engineering, IIT - Jodhpur
|
| 16:15 - 16:45 | Grand Ballroom | | 4X Runtime Improvement on Full Chip ICV LVS Checking on Advanced Technology Node [More Info]
Speaker: Anand Kumaraswamy, GLOBALFOUNDRIES
|
| 16:15 - 17:00 | Jamavar | | NanoTime to Validate the Timing and Noise of Custom Memory and Analog Mixed Signal Blocks [More Info]
Speaker: Nishath Verghese, Synopsys
|
| 16:15 - 17:15 | Kamal | | Billion Cycle Debug Challenge; Benefits of System Level Debug [More Info]
Speaker: Ravi Prakash Gupta, Sr. Application Engineer, Synopsys
|
| 16:30 - 17:15 | Turret Boardroom | | Citius, Minutus, Exactus: Olympian Challenges in Machine Learning [More Info]
Speaker: Tathagata Bhowmick, Synopsys
|
| 16:45 - 17:15 | Grand Ballroom | | Drive Faster Signoff Closure and Eliminate ECO Iterations with ECO Fusion [More Info]
Speaker: Raj Sekhar Bochkar, Sr. Staff Application Engineer, Synopsys
|
| 17:15 - 17:30 | No location | | Best Paper Awards and Lucky Draw [More Info] |
