| 7:30 am - 5:00 pm | Royal Ballroom Foyer | | Registration [More Info] |
| 9:15 am - 10:15 am | Royal Ballroom | | Synopsys Keynote: New Technologies Driving Innovation [More Info]
Speaker: Chi-Foon Chan, President and co-Chief Executive Officer, Synopsys
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| 10:15 am - 10:45 am | Royal Ballroom | | Industry Keynote: Semiconductors: Strategic Enabler of New Age Technologies [More Info]
Speaker: Vivek Sharma, India Managing Director , STMicroelectronics
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| 11:15 am - 11:45 am | Royal Ballroom 3 | | Deep State Bug Hunting using VCFormal for Post Silicon Bug Reproduction [More Info]
Speaker: Ipshita Tripathi, Qualcomm
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| 11:15 am - 12:00 pm | Royal Ballroom 1 | | Fusion Compiler A New Era in High-Performance Digital Design [More Info]
Speaker: Sanjay Bali, Synopsys
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| 11:15 am - 12:00 pm | Royal Ballroom 2 | | Shift Left TestMAX Flow and X-tolerant Logic BIST Solution for Automotive ICs [More Info]
Speaker: Thryambak Chandilya, Synopsys
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| 11:15 am - 12:00 pm | Maple & Oak | | Synopsys Custom Design Vision [More Info]
Speaker: Avina Verma, Synopsys
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| 11:45 am - 12:15 pm | Royal Ballroom 3 | | Applying Formal Beyond Connectivity Checks at SoC [More Info]
Speaker: Abhinav Gaur, NXP
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| 12:00 pm - 12:30 pm | Maple & Oak | | Custom Compiler Based Analog Layout Methodology for High Productivity [More Info]
Speaker: Deep Shikha, STMicroelectronics
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| 12:00 pm - 12:30 pm | Royal Ballroom 1 | | Improving PPA through Localized Flexible Power Grid using Integrated IC Compiler II and Redhawk Flow [More Info]
Speaker: Gurbax Singh Sohi, Qualcomm
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| 12:00 pm - 12:30 pm | Royal Ballroom 2 | | TestMax Fusa - Functional Safety [More Info] |
| 12:15 pm - 12:45 pm | Royal Ballroom 3 | | Innovative Microarchitectural Techniques to Accelerate Reset Domain Crossing Signoff with Spyglass [More Info]
Speaker: Kriti Garg, NXP
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| 12:30 pm - 1:00 pm | Royal Ballroom 1 | | Combating Congestion in Floorplans with Highly Skewed Aspect Ratio and Rectilinear Shape [More Info]
Speaker: Suraj Pradhan, NXP
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| 12:30 pm - 1:00 pm | Maple & Oak | | Creating SDL Compliant and Electrically Aware Layouts to Gain Design Efficiency [More Info]
Speaker: Mona Babbar, STMicroelectronics
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| 12:30 pm - 1:00 pm | Royal Ballroom 2 | | Effective Implementation of Shared CODEC to Reduce Overall DFT Pin Requirement [More Info]
Speaker: Ramesh Devani, Einfochips
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| 2:00 pm - 2:30 pm | Royal Ballroom 1 | | DC-NXT [More Info]
Speaker: Philip Issac, Synopsys
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| 2:00 pm - 2:30 pm | Royal Ballroom 3 | | Importance of Capturing the Right Intent in IP Abstract Model for Hierarchical CDC Flow [More Info]
Speaker: Ashish Soni, STMicroelectronics
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| 2:00 pm - 2:45 pm | Maple & Oak | | Analog Fault Simulation - A Systematic Approach to Ensuring Functional Safety and Low Defect Rate in Automotive ICs [More Info]
Speaker: Ravi Tembhekar, Synopsys
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| 2:00 pm - 2:45 pm | Royal Ballroom 2 | | PrimeTime Productivity Improvement DMSA Best Practices & IMSA Roll-up Reporting [More Info]
Speaker: Vikas Choudhary, Synopsys
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| 2:30 pm - 2:45 pm | Royal Ballroom 1 | | Taming Compute Intensive Cores for Predictable Convergence using DC-NXT [More Info]
Speaker: Arpit, NXP
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| 2:30 pm - 3:15 pm | Royal Ballroom 3 | | Functional Safety (ISO 26262) Verification for Automotive SoCs [More Info]
Speaker: Sesha Sai, Synopsys
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| 2:45 pm - 3:15 pm | Royal Ballroom 1 | | Deciphering Enigma of Architectural Challenges using Novel Synthesis Methodology [More Info]
Speaker: Sakshi Garg, STMicroelectronics
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| 2:45 pm - 3:15 pm | Maple & Oak | | Optimizing Design and Simulation Run Times of Custom Analog Mixed-Signal Circuits using Synopsys' Simulation and Analog Environment (SAE) [More Info]
Speaker: Pramod Baliga K, AMD
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| 2:45 pm - 3:15 pm | Royal Ballroom 2 | | Timing Aware Remodeling of Clock Tree to Improve Common Clock Path for Setup and Hold Fixing [More Info]
Speaker: Atul Jha, Qualcomm
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| 3:15 pm - 3:45 pm | Maple & Oak | | Accurate and Fast Parasitic Extraction with Rapid3D SMC Flow Enabling IP Development [More Info]
Speaker: Chandan Singh, STMicroelectronics
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| 3:15 pm - 3:45 pm | Royal Ballroom 1 | | Divide and Conquer Strategy to Tackle Seemingly Unsolvable 25M+ Gate Design with Hybrid Hierarchical and Flat Approach [More Info]
Speaker: Trishit Dutta, NXP
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| 3:15 pm - 3:45 pm | Royal Ballroom 2 | | New Approach to Insert Register Slices using Primetime A Method used to Fix Yield Loss Caused Due to Long High Speed Source Synchronous Bus MCP0 Paths [More Info]
Speaker: Deep Gupta, NXP
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| 3:15 pm - 3:45 pm | Royal Ballroom 3 | | Safety Verification in Image Processing!! Gotchas to Avoid and ZOIX to the Rescue [More Info]
Speaker: Amit Jain, NXP
Mayank Agarwal, NXP
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| 4:00 pm - 4:30 pm | Royal Ballroom 1 | | Achieving Predictable Timing and Comprehensive DRC Closure using ICV/IC Compiler II for Large Hierarchical Design in 16 FinFET [More Info]
Speaker: Ankit Jain, NXP
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| 4:00 pm - 4:30 pm | Royal Ballroom 3 | | Methodologies for Handling Analog PHY Models for ADAS SoCs on Zebu Emulation [More Info]
Speaker: Prateek Sikka, NXP
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| 4:00 pm - 4:45 pm | Maple & Oak | | Extending Pre-Silicon FCS (Full Chip SPICE) Verification to Multi Die and Multi Technologies [More Info] |
| 4:00 pm - 4:45 pm | Royal Ballroom 2 | | Machine Learning Accelerated ECO and Latest Advances with PrimeTime-ADVPlus [More Info]
Speaker: Arundas Haridas, Synopsys
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| 4:30 pm - 5:00 pm | Royal Ballroom 1 | | Accelerating Physical Verification Productivity with IC Validator NXT [More Info]
Speaker: David De Marcos, Synopsys
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| 4:30 pm - 5:15 pm | Royal Ballroom 3 | | Directed Verification Framework for Ethernet Boot [More Info]
Speaker: Abhijit Das, NXP
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| 4:45 pm - 5:15 pm | Royal Ballroom 2 | | Novel Methodology to Achieve Higher Frequencies using PrimeTime DMSA Cockpit [More Info]
Speaker: Jasmine Gulati, Qualcomm
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| 5:00 pm - 5:15 pm | Royal Ballroom 1 | | Achieving Seamless Physical Verification Closure on Advanced Nodes using IC Validator: A FinFET User Experience [More Info]
Speaker: Avdhesh Vaid, STMicroelectronics
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| 5:30 pm - 6:00 pm | Royal Ballroom | | Best Paper Awards and Lucky Draw [More Info] |
