| 12:00 - 13:00 | Marble Corridor/Foyer | | Lunch [More Info] |
| 12:00 - 18:00 | Atrium | | Registration [More Info] |
| 13:00 - 13:15 | Munich 1 | | Welcome to SNUG Europe 2019 [More Info]
Speaker: Peter Rothenaicher, Synopsys
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| 13:15 - 14:15 | Munich 1 | | Keynote: Early System-Level Resilience Evaluation for Embedded Systems [More Info]
Speaker: Professor Ulf Schlichtmann, Chair of Electronic Design Automation, Department of Electrical and Computer Engineering, Technical University of Munich
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| 14:45 - 15:30 | Frankfurt | | Characterization: What is LVF and How to Cook it [More Info]
Speaker: Olga Gudkova, Synopsys
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| 14:45 - 15:30 | Munich 1 | | Pervasive Concurrent Clock and Data (CCD) [More Info]
Speaker: Tobias Bjerregaard, Synopsys
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| 14:45 - 16:15 | Bangkok 1 & 2 | | Introduction to Functional Safety for Automotive [More Info]
Speaker: Jörg Richter, Synopsys
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| 15:30 - 16:15 | Munich 1 | | Clock Tree Synthesis (CTS) Debug in IC Compiler II [More Info]
Speaker: Frank Schlegel, Synopsys
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| 15:30 - 16:15 | Frankfurt | | Fight Pessimism with Statistics [More Info]
Speaker: Gernot Gall, Synopsys
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| 16:45 - 17:15 | Munich 1 | | Maximizing your Productivity in the IC Compiler II GUI [More Info]
Speaker: Dan Guilin, Synopsys
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| 16:45 - 17:45 | Bangkok 1 & 2 | | Advancements in Debug Technology [More Info]
Speaker: Jens Dickel, Synopsys
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| 16:45 - 17:45 | Frankfurt | | Getting your $$$ from Verilog-A [More Info]
Speaker: Peter Grove, Dialog Semiconductor
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| 17:15 - 18:15 | Munich 1 | | Fast, High-Quality Interconnect Pre-Routing with IC Compiler II [More Info]
Speaker: Dan Guilin, Synopsys
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| 17:30 - 18:15 | Bangkok 1 & 2 | | Case Study on Automation of SoC Verification Environment [More Info]
Speaker: Jukka Heikkila, Synopsys
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| 17:45 - 18:15 | Frankfurt | | Utilizing System Verilog in Conjunction with Verilog-A for Mixed Signal Verification with Behavioral Models - an Alternative to Verilog AMS! [More Info]
Speaker: Peter Thompson, Synopsys
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| 18:45 - 22:00 | TBD | | Social Evening Event [More Info] |
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| 08:00 - 09:00 | Marble Corridor/Foyer | | Breakfast [More Info] |
| 08:00 - 16:30 | Atrium | | Registration [More Info] |
| 09:00 - 10:15 | Munich 1 | | Welcome and Keynote - Keynote: "High Impact Innovation" [More Info]
Speaker: Sassine Ghazi, Synopsys
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| 10:30 - 11:00 | Munich 1 | | Accelerating Physical Verification Productivity with IC Validator NXT [More Info]
Speaker: Jonathan White, Synopsys
Speaker: David DeMarcos, Synopsys
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| 10:30 - 11:00 | Tokyo and Istanbul | | Analog Fault Simulation: A Systematic Approach to Ensuring Functional Safety and Low Defect Rate in Automotive IC [More Info]
Speaker: Uwe Trautner, Synopsys
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| 10:30 - 11:00 | New York | | NVM Embedded Memories Design Enablement Flow with Synopsys Platform [More Info]
Speaker: Laura Capecchi, STMicroelectronics
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| 10:30 - 11:00 | Frankfurt | | Software and UVM Driven SOC Verification [More Info]
Speaker: Youssef Bakrim, Sondrel
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| 10:30 - 11:00 | Bangkok 1 & 2 | | Using IC Validator Sign-off tool within (Fusion) IC Compiler II on a Large 16FFC SOC Automotive Design [More Info]
Speaker: Quentin Gunn, NXP Semiconductors
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| 10:30 - 11:00 | Munich 2 | | Using SysML for Modeling and Generation of Virtual Platforms [More Info]
Speaker: Aljoscha Kirchner, Robert Bosch GmbH
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| 11:00 - 11:30 | Frankfurt | | Drive UVM VIPs by C Code Running on the Integrated ARC [More Info]
Speaker: Gilberto Muzzi, EASii-IC
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| 11:00 - 11:30 | Munich 2 | | Exhaustive Datapath Verification with VC Formal [More Info]
Speaker: Laureano Carrasco, Synopsys
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| 11:00 - 11:30 | Munich 1 | | Power Optimization Techniques for Ultra-low Power IoT Design Implementation [More Info]
Samuel Boscher, STMicroelectronics
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| 11:00 - 12:00 | New York | | Making Sure Your Design is Robust Enough Against Variations - Efficient Monte Carlo Solution with HSPICE, FineSim and CustomSim [More Info]
Speaker: Uwe Trautner, Synopsys
Speaker: Uwe Trautner, Synopsys
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| 11:00 - 12:00 | Tokyo and Istanbul | | New Features for Automotive Functional Safety in Synopsys RTL-to-GDSII Flow [More Info]
Speaker: David Kingston, Synopsys
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| 11:00 - 12:00 | Bangkok 1 & 2 | | Superior Reliability Checking with IC Validator PERC and Python [More Info]
Speaker: Jonathan White, Synopsys
Speaker: Jeff Byrd, Synopsys
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| 11:30 - 12:00 | Munich 1 | | GLOBALFOUNDRIES Digital Implementation of a 2.5D Silicon Interposer for Multi-Die, Module Integration [More Info]
Speaker: Premsai Kidambi Venugopalan, GLOBALFOUNDRIES
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| 11:30 - 12:00 | Frankfurt | | Methodologies to Mitigate Complexity of Pre-Silicon Verification Architectures [More Info] |
| 11:30 - 12:00 | Munich 2 | | Regression Testing of Hardware-Dependent Software Drivers on the Virtual Platform of AURIX 2G [More Info]
Speaker: Bernd Pfaff, Continental Automotive GmbH
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| 12:00 - 13:25 | Atrium | | Networking Lunch [More Info] |
| 13:25 - 13:55 | Munich 1 | | Keynote:"Unleash your Innovations in AI, 5G and Automotive Applications with the Latest Technology from TSMC" [More Info]
Speaker: Dan Kochpatcharin, Senior Technical Director, TSMC
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| 14:00 - 14:30 | Bangkok 1 & 2 | | Can DFTMAX™ Ultra Compression Results be Improved by Reducing the Effects of Decompressor Dependencies? [More Info]
Speaker: Richard Illman, Dialog Semiconductor
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| 14:00 - 14:30 | Munich 2 | | Creating Debug-Friendly and User-Defined HAPS FPGA Platform [More Info]
Speaker: Svetlana Frolova, R&D Center ELVEES
Speaker: Fedor Putrya, R&D Center ELVEES
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| 14:00 - 14:30 | New York | | Custom Compiler Ecosystem at STMicroelectronics [More Info]
Speaker: François Lémery, STMicroelectronics
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| 14:00 - 14:30 | Tokyo and Istanbul | | Investigating the Avoidance of Certitude Qualification Closure when Mutations are Detected only on Secondary Effects [More Info]
Speaker: James Buckingham, Infineon Technologies
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| 14:00 - 14:30 | Munich 1 | | Using IC Validator in GLOBALFOUNDRIES 22FDX® Flow for Physical Design Verification [More Info]
Speaker: Herbert Preuthen, GLOBALFOUNDRIES
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| 14:00 - 14:45 | Frankfurt | | Formality 2018.06 and 2019.03 Technology Update [More Info]
Speaker: Rod Carroll, Synopsys
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| 14:30 - 15:00 | Tokyo and Istanbul | | A Practical Approach to Qualify the Functional Verification of Firmware Design [More Info]
Speaker: Zhaojun Shao, Infineon Technologies
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| 14:30 - 15:00 | Bangkok 1 & 2 | | How to Conciliate IC Compiler II Clock-tree Synthesis with DFT-Compiler Scan Shift? [More Info]
Speaker: Cédric Escallier, STMicroelectronics
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| 14:30 - 15:00 | New York | | Layout Post Processing with Synopsys PyCell Studio [More Info]
Speaker: Ilya Temnikov, LFoundry
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| 14:30 - 15:30 | Munich 1 | | Fusion Compiler : Digital (RTL-to-GDSII) Design Implementation [More Info]
Speaker: Frank De Meersman, Synopsys
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| 14:30 - 15:30 | Munich 2 | | Usage of ZeBu for Hybrid Verification of Automotive SoCs [More Info]
Speaker: Caaliph Andriamisaina, CEA
Speaker: Fabian Delguste, Synopsys
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| 14:45 - 15:30 | Frankfurt | | PrimeTime 2019.03 Release Overview and Accelerated Design Closure with PTECO [More Info]
Speaker: Simon Bloyce, Synopsys
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| 15:00 - 15:30 | New York | | Bringing Mixed Signal Verification to Analog Designers [More Info]
Speaker: Stefan Frank, Creative Chips
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| 15:00 - 15:30 | Tokyo and Istanbul | | Memory Test & Repair and Hierarchical Test of Automotive FinFET based SoC’s [More Info]
Speaker: Yervant Zorian, Synopsys
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| 15:00 - 15:30 | Bangkok 1 & 2 | | Transition Fault Pattern Optimization for Mixed Signal SOCs using Low Power Budget Options [More Info]
Speaker: Pascal Raga, STMicroelectronics
Speaker: Cédric Escallier, STMicroelectronics
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| 16:00 - 16:30 | Tokyo and Istanbul | | Advancing FW Code Coverage with Verdi HW/SW [More Info]
Speaker: G. Hametner, Infineon Technologies
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| 16:00 - 16:30 | Munich 2 | | An Optimization of RDC Structural Checks Flow [More Info]
Speaker: Julien Faucher, STMicroelectronics
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| 16:00 - 16:30 | Munich 1 | | GLOBALFOUNDRIES 22FDX® Area-Efficient Implementation Flow to Mix 8-Track and 7.5-Track Std-Cells in ICC2 [More Info]
Speaker: Stefan Block, GLOBALFOUNDRIES
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| 16:00 - 16:30 | New York | | VCS-AMS© UPF Mixed Signal Flow for STMicroelectronics Bluetooth Low Energy Design Verifications [More Info]
Speaker: Cécile Specq, STMicroelectronics
Speaker: François Ravatin, STMicroelectronics
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| 16:00 - 17:00 | Bangkok 1 & 2 | | DFT Shifts Left to Accelerate Time to Results! [More Info]
Speaker: Salvatore Talluto, Synopsys
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| 16:00 - 17:00 | Frankfurt | | Where are we on the Road to Artificial Intelligence in Chip Design? [More Info]
Speaker: Thomas Andersen, Synopsys
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| 16:30 - 17:00 | New York | | A Hierarchical UPF Implementation in Analog Mixed Signal Verifications at SoC Level [More Info]
Speaker: Gianluca Farabegoli, STMicroelectronics
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| 16:30 - 17:00 | Munich 1 | | Low-Voltage Adaptive Body Bias Aware Library Characterization using SiliconSmart [More Info]
Speaker: Dennis Walter, Racyics GmbH
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| 16:30 - 17:00 | Tokyo and Istanbul | | VC Apps Meets Python [More Info]
Speaker: Aditya Hendra, Axis Communications AB
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| 16:30 - 17:00 | Munich 2 | | Why is Design Constraints (SDC) Validation Critical at RTL? [More Info]
Speaker: James Gillespie, Synopsys
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| 17:00 - 18:00 | Marble Corridor/Foyer, then Munich 1 | | SNUG Pub and Awards [More Info] |
