Automotive systems have stringent functional safety requirements as defined by the ISO 26262 standard. Soft errors are hardware disturbances caused by external factors such as radiation that lead to bit-flip in registers which can cause catastrophic failures during the operation of a safety-critical electronic device.

 

This tutorial shows how static analysis of soft error propagation can be used either at RTL or gates to calculate the probability of avoiding a failure as reflected in the Single Point Fault Metric (SPFM). You will learn how to run a fast analysis to identify and address hotspots early in the design cycle and swap functional safety critical registers with "hardened" cells.

 

Due to performance and capacity advantages, Emulation allows validation of billion gate design running billion cycle applications. To debug an issue in such a system, poses several challenges due to amount of debug data generated. Traditional iterative waveform level debug is no longer effective as the sole means to find root causes for incorrect behavior. Even a million cycle capture is a small fraction of the total test length and multiple iterations are required to find the window of interest. In case of transient failures of the emulation setup, such methods can easily run in circles and finding the failure is becoming unpredictable.

 

In this tutorial, we present how to use ZeBu to cut debug time after a failure has been reported during a multi-billion cycles regression. Through unlimited streaming of the designs system log all key information is captured during the emulation run. From there the user can quickly determine the window of interest and using the proven ZeBu replay technology and powerful Verdi debug, the bug can be root caused quickly. We summarize the tutorial with real world examples to show the actual benefit of the ZeBu approach.

As device and interconnect geometries shrink with every process, process variation plays an increasingly important role. In particular, the impact of parasitic RC variation of interconnect becomes more critical.

 

Traditional methods of realizing the extraction and simulation of parasitic RC variation rely on Parasitic Extraction (PEX) runsets that realize one corner at a time, often with all interconnects skewing to the same corner at once. For example, all interconnect may realize maximum capacitance in the same netlist. These traditional methods are overly conservative and sacrifice performance for unnecessary guard band.

 

In this paper, we will discuss the StarRC Parameterized Spice Netlisting capability. This capability allows the user to reduce the pessimism in traditional PEX corners, by allowing for per level settings of interconnect RC variation in simulation, and hence enabling for a Monte Carlo simulation to determine the optimal PEX corners for a given circuit.

 

An overview of the tool capability and required collateral will be provided, and use models, with results, will be described.

 

In general, for any change in RTL, a functional ECO is implemented directly in the place and route netlist. This breaks the ASIC flow. The ECO is rolled back to the synthesized netlist to re-affirm the ASIC flow.

 

After rolling back the ECO, re-synthesizing the new RTL and comparing the new netlist with the old netlist is not recommended for following reasons: 

• Most RTL have some don't care spaces and different synthesis runs can optimize the don't care spaces differently. The equivalence checking between old netlist and new netlist may fail despite both netlists being logically equivalent. 
• Two different synthesis netlists may have different implementation architecture of large multipliers. In such cases, the equivalence checking may result in an "inconclusive" verification. 

We propose a method with Formality Ultra such that the new synthesized netlist is referred directly to implement functional ECO in old synthesized netlist. This flow allows an optimal logic in the functional ECO. The equivalence check between new RTL and modified old synthesized netlist is performed using original SVF, modified SVF and mapped SVF. With the recommendation in this paper, the functional changes are carried forward in short turnaround time without breaking the ASIC flow.

 

This paper discusses the learning experience and challenges of a new IC Compiler II user for chip-level place-and-route of a production chip. It starts out with the comparative pros and cons of IC Compiler II and the reasoning behind choosing ICC Compiler II. Then it dives deeper into the flow and issues that were faced as a new user and how those were resolved.

 

The topics include library preparation, chip-level UPF, floorplanning, PG, Flip-Chip and bump-routing, pin-assignment (of PnR blocks) and chip-level integration. In each of these stages, there were some challenges related to using a new PnR tool. With Synopsys AE support and intelligent design techniques all the challenges were resolved or worked-around and we had a successful and timely tapeout.

 

The increasing complexity of memory designs using high-speed signal interfaces makes functional verification difficult. These memory designs contain mixed-signal elements and many repetitive circuits. In order to reduce the simulation time and computing resources required, the netlist used for full-chip simulation is typically post-processed to decrease the number of top-level design instances of the repetitive circuits. Each of these instances are also connected to a number of memory core-cell models to enable end-to-end memory operations in simulation.

 

This paper presents a method that dynamically configures the SPICE netlist, incorporates a SystemVerilog memory core-array model into the device under test and integrates the memory model with a UVM environment. This method allows running different netlist configurations without post-processing the netlist, reduces the simulations overall memory requirement and contains the benefits of having a digital top-level testbench environment.

 

Synopsys tools have been highly optimized on traditional HPC infrastructure for decades. The Cloud has components that are today similar to HPC. However, it also has differences that favor web scale applications. Synopsys is thus working to enable technologies within our tools that can harness the Cloud today. In this talk, we will discuss what Synopsys is doing to help customers through the cloud transition.

 

While our tools have been cloud-ready in the area of compute parallelization for almost a decade, we are enhancing the tools to support easy workload transfers and data parallel architecture. We describe the models of cloud usage, and how our tools can be used in these scenarios.

 

We will share our long-term roadmap for targeting cloud-native architectures - including containers, reduced tool footprint, scaling with elasticity and reduced dependence on traditional HPC components.

As designs and power domain specs constantly grow in size and complexity, the timing signoff process requires an increasing number of runs to model all voltage permutations across the various power rails. Different voltage levels need to be analyzed both within domains and across domains. When a product is required to function with best power/performance across a wide range of voltage operation points, we face an additional level of complexity in meeting different frequencies for different voltage settings.

 

Due to technical limitations of resources and tools capacity, multiple STA runs introduce a great challenge in timing convergence under a tight project timeline. This session presents a new SMVA (Simultaneous Multi Voltage Analysis) solution that is based on UPF definitions, and allows customized setting of pre-known limitations in order to get all the required scenarios data without redundancies, providing an accurate and optimized analysis for multi-voltage designs.

 

 

Modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters. PPA (performance/power/area) estimates for these components are highly desirable during early design phases long before NoC gate level netlist is synthesized. At this stage, a NoC component is a soft module, described by a set of architectural parameters, like the bit width of ingress and egress ports, number of virtual channels, etc.

 

The proposed approach attempts to predict the PPA behavior of NoC components based on machine learning non-linear regression algorithms. The system consists of several layers. At the bottom, Synopsys Design Compiler is used to synthesize a NoC component with one combination of input parameters (features) and capture its characteristics. This result becomes a data point in a training set. When it gets sufficiently large, this set is being used for training fast models predicting PPA for components with parameter values not exercised during the training. These models can be plugged into a NoC design tool assisting the user with feasibility and what-if analysis.

 

 

Demand for ICs which can be used in higher ASIL rating systems are rapidly increasing in conjunction with the increased demand in semi-autonomous and autonomous driving systems. LBIST is a very effective tool in catching random hardware failures in such ICs and can be used to increase latent point failure metric (LPFm) to achieve higher ASIL ratings.

 

In this paper, we will be discussing the LBIST implementation methodology being adopted for a power management integrated circuit (PMIC), which has been designed according to ISO26262 standard and will be used as part of camera module in automotive applications. In this design, higher than 80% LBIST coverage and less than 10mS LBIST runtime is required . It is required to have separated LBIST for 2 individual blocks (150 andamp; 8k registers each) which has independent scan chain controlled by one master module. The paper discuss:

• Challenges faced during lightweight lbist implementation for the small cores and how they were addressed
• Test points were used instead of core-wrapping for the lightweight lbist solution 
• SpyGlass Test-point insertion to optimize the pattern count and coverage 
• LBIST simulation techniques to expedite simulation debugging 

The paper concludes with the achieved LBIST coverage and pattern count with the above implementation.

Fault Injection, relegated to a niche for many decades, has suddenly become once again a mainstream activity because of the requirements of functional safety. There are situations where the validation of safety metrics for a certain safety architecture (e.g. a core protected by a software test) requires an extensive injection of faults and their grading to determine whether they are safe or dangerous and whether they are detected or not by the safety measures. Of course the simulation of complex applications (e.g. the boot of a device) with large fault lists may still be unfeasible, despite the amount of hardware dedicated to it. This is where exploiting emulation platforms may help beating the complexity barrier. The pre-silicon emulation of functionalities not easily simulated is a popular practice. Exploiting the already existing emulation environment for these functions and adding a fault injection layer to it makes it possible to perform fault injection campaigns that would otherwise be unfeasible.

 

In this paper we explore the experience and the methodology we built, comparing results with respect to the more traditional simulation-based approach.

 

CustomSim Circuit Check (CCK) delivers quick, and vast static, as well as, dynamic analysis that uncover design weaknesses to ensure a designs robustness and reliability. CCK offers circuit checks including device parametric checks, ERCs, timing checks, and signal integrity checks that help users uncover performance and functional issues at early stages in design without the need to use expensive simulations.

 

As the technology advances, circuit geometries become smaller, hence, wire interconnects become closer to each other which causes an increase of cross-coupling capacitance effects. In this paper, we cover the use of a recent CCK feature that handles crosstalk in custom design by gauging the effect of coupling capacitance on circuits functionally. The command checks for value and width of glitches are induced by the switching signals of the attacking neighbors, and reported on all nets with coupling capacitors. This helps isolate risky path or nets, and allows the design to perform more verification and optimization to ensure proper functionality.

 

Driven by increasing hardware and software complexity, designers continue to accelerate their System On Chip (Soc) design cycles. To keep up with the accelerated design cycles, it is essential that design verification remains productive by using the right set of tools. This paper explains how NVIDIA set up a methodology for efficiently debugging SystemVerilog assertions by leveraging Synopsys' High Performance Prototyping Solution (HAPS) and Verdi debug platforms together on our latest RTL designs.

 

In this paper, we will cover the following topics:

Early, accurate power estimation for SoC designs has long been a goal of ASIC and system designers. To address this need, EDA vendors have developed tools for RTL power estimation, in-synthesis power analysis, and emulation power profiling. These tools attempt to compensate for the lack of comprehensive design information using methods such as synthesis estimates, average-power power analysis engines, and activity extrapolation or propagation heuristics using non-simulation activity estimates, or zero-delay RTL activity.

 

To avoid the accuracy concerns inherent in RTL power analysis methods, we developed a flow using PowerReplay, PrimeTime PX/PrimePower, and Design Compiler. This flow uses the actual gate-level design netlist, accurate gate-level zero-delay simulations, and quality, sign-off power analysis engines. This flow provides more accurate power analysis results at a much earlier point in the design flow. With this flow, engineers have more confidence in the power numbers that they use for comparing architecture choices, reviewing improvements made to RTL coding, and providing power consumption values to system-level architects and back-end designers. This session will present the flow we developed, important flow enhancements we added as well as several best-practices.

Ansys RedHawk is an industry standard power noise and reliability sign-off solution for SoC designs. IC Compiler II is enhanced to perform analysis and fixing using Ansys RedHawk. The tutorial describes an overview of IC Compiler II /RedHawk analysis fusion and the various types of analysis, including static, dynamic, EM and resistance analysis. The tutorial further describes the fixing and optimization techniques, including missing via detection/fixing, PG augmentation and IR aware placement.

 

The target audience is users performing physical design implementation and reliability analysis, including IR drop and EM analysis.

The growth of data traffic for achieving performance-intensive tasks is driving the need for new data center architectures, Ethernet PHY IP and interconnects. Hyperscale data centers are shifting to faster, flatter, and more scalable network architectures. High-speed Ethernet solutions are transitioning to the PAM-4 modulation scheme, allowing high bandwidth and long reaches. 400G Ethernet interconnects are based on length requirements, density, form factor, and power consumption.

 

This presentation details the new modulation schemes and Ethernet PHY IP architecture that can help you meet your design requirements for 400G+ hyperscale data center SoCs.

Design Verification (DV) engineers are often intrigued by how Machine Learning (ML) can help with their daily tasks, but may not know how to get started.

 

The first half of this presentation walks through a brief background on ML and, in particular, how ML can be applied in the DV field. In this section we introduce Verdi technologies that powered our experiments, Verdi Learn and Verdi Automatic Root Cause Analysis (Auto RCA). We share our experience on how best to use these Verdi technologies. The second half of the presentation reflects on Broadcoms experience and results using these technologies.

 

This presentation will shed light on the process of deploying an ML engine in an actual problem solving capacity. The goal of this presentation is to create a better understanding of how ML can be used in the DV field, and to inspire other creative ways of applying Verdi Learn and Verdi Auto RCA on the wide variety of problems and tasks to be tackled.

NexGen SoCs with advanced graphics, computing and Artificial Intelligence capabilities are posing new unseen challenges in verification. Designers and verification engineers using static verification technologies like LP/CDC/RDC often complain about the large number of violations generated by these tools. Efficiently debugging and root-causing issues becomes a huge challenge.

 

This tutorial will talk about the present application of deterministic and machine learning-based techniques to automatically identify the accurate root causes for related group of violations. This will significantly help to reduce the overall TAT for verification closure ensuring a shift-left and also make sure that subtle bugs do not escape into silicon.

 

The JEDEC LPDDR5/4/4X memory standards primarily target mobile applications, providing high bandwidth memory access and numerous low-power states for power savings during idle time. Unlike DDR5/4/3, each independent channel is 16 bits wide and applications such as digital home/office, laptops, SSDs, AI, etc. typically connect to these memories in unintended ways, such as operating two 16-bit channels in lock-step.

 

This presentation explains the different ways designers can connect to LPDDR5/4/4X SDRAMs and outlines the characteristics of each configuration including signal integrity trade-offs.

While already delivering industry-leading products at the performance and reticle-size limit, the accelerating demands associated with hyper-scale data-center, highly-configurable networking, and artificial intelligence are necessitating even higher computational-density than even the most advanced, Moore-driven-scaling-based processes can provide.

 

Three-dimensional (3D) IC and 2.5D interposer systems are the most promising technologies that are enabling Xilinx to deliver the density, latency, and power consumption demands to meet the ever-expanding challenges of todays hyper-converged systems. With flexible system-level scaling a core requirement to meet the varying demands of Xilinxs family-of-products solutions, TSMCs broad offering of 2.5D CoWoS, InFo, SoIC, and 3D Wafer-on-Wafer-direct-stacking provide for a wide variety of solutions to address the growing integration challenge.

 

This paper will provide insight into some of Xilinxs unique and FPGA-specific demands and highlight Synopsys key new technologies and methodologies that exploit these exciting and challenging silicon processes. As a platform-wide problem, we will share insights into the many unique methodologies that includes IC Compiler II for multi-die and interposer floor-planning, physical implementation and optimization. StarRC for parasitic extraction of CoWoS and WoW/SoIC designs, PrimeTime for a complete system, multi-die, and multi-process static-timing analysis and IC Validator that supports full-system DRC and LVS verification.

There are at least six different Finite State Machine (FSM) design techniques that are commonly taught, one with combinatorial outputs and five with registered outputs. This paper will describe three of the FSM design techniques: (1) 2-Always Block Style with combinatorial outputs, (2) 1-Always Block Style with registered outputs, and (3) 3-Always Block Style with registered outputs.

 

This paper establishes measurement techniques to determine good coding styles and also shows synthesis results for both ASIC and FPGA designs. Multiple benchmark FSM designs are used to measure coding style and synthesis efficiency.

 

The other three FSM design styles will be described in one or more follow-on papers.

Formal Verification is becoming an integral part of modern verification environments. With increasing adoption of Formal, design and verification teams are setting up Formal regressions similar to what we have seen for simulation for the past few decades. Across consecutive nightly Formal regression runs, generally there is very little incremental change in RTL and assertions; this represents a great opportunity for machine learning technologies to learn from one Formal regression run and leverage it for the next regression run.

 

VC Formal RMA (Regression Mode Accelerator) leverages machine learning technologies to provide significant performance boost for Formal regressions. The same capability can also be used to accelerate designer/verification engineers' driven interactive Formal verification.

 

In this tutorial, we start with a brief introduction to machine learning techniques, we will talk about RMA, its use models and share information on a few customer case studies.

 

Clocking structures are at the heart of every design, with more complexity these days than ever. Ever increasing design sizes, merging of test modes for in-design test and advanced power savings techniques, all add to that complexity.

 

This tutorial will walk the attendee through a typical approach to CTS debug. Both reporting and interactive exploration techniques will be covered for several common clocking issues with examples provided for each.

 

The target audience is ICC II users who do block level physical design implementation. Attendees should expect to gain broader understanding of how to apply a number of ICC II GUI and reporting features for use in understanding common, block level CTS issues that tool users will regularly encounter. The presentation will include some best practices for common block level tasks as well as examples of visualization on design data.

New Radio Access Technology (NR) requirements with higher peak data rates and broadening variety of use cases lead to drastically increasing gaps between lowest and highest device performance and power operating points. It becomes more challenging to meet power and performance KPI targets across broad range of applications with one architecture. Post-RTL and post-silicon optimization efforts become more resource and time consuming, increasing risks to delivery schedule.

 

This presentation outlines pre-RTL NR SoC architecture exploration with simultaneous optimization of power, HW and SW performance KPIs.

 

The case study is focusing on power architecture and power management efficiency exploration and implementation requirements definition while meeting HW and SW performance KPIs across broad range of use cases.

New process technologies enable designers to deliver more performance, but at the cost of significantly more design effort. Challenges introduced by the latest process technologies include the divergence between pre-layout and post-layout simulations, high interconnect parasitics, and the need to design for reliability.

 

During this presentation, you will hear from the Synopsys Mixed Sigal IP team about our high-speed SerDes design projects key findings, illustrating how designers can optimize their design methodology to overcome challenges, while meeting aggressive schedules. We will also describe some of the key features of the Synopsys Custom Design Platform that were helpful on this project.

Virtual platforms, due to their early availability and unique controllability and observability of the system operation, allow device software to be developed ahead of hardware availability and tested with full visibility of the hardware software interactions in the system. With the introduction of Synopsys' PCIe Virtual I/O technology, you can now connect a virtual prototype of your device to a PCIe based host system implemented as a virtual machine, running the guest OS of your choice, as if it was a physical device. This capability enables the development of host side drivers of your PCIe device, run applications that exercise the device on the target OS and end-to-end testing of such systems.

 

In this tutorial, we will show how PCIe Virtual I/O capability can be used with a virtual prototype of an SSD device to create a fully virtual solution for end-to-end software development and test. Based on PCIe benchmark application, we will demonstrate the execution of end-to-end use cases, thus improving software stability and test coverage, as well as validating overall system architecture. We will also demonstrate the unique debugging capabilities to accelerate software development for complex PCIe based SSD devices.