| row-start col-xs-12 row-end agenda-header-section |
| row-start col-xs-12 row-end agenda-section agenda |
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Artificial Intelligence | |
Automotive |
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Cloud | |
Custom Implementation & AMS |
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Custom Implementation & AMS | |
General Sessions |
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IP | |
Lunch & Learn |
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Networking Opportunities | |
Physical Implementation |
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RTL Implementation | |
Signoff & Characterization I |
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Signoff & Characterization II | |
Test |
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User Content Reviewed by the Technical Committee | |
Verification Continuum I |
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Verification Continuum II | |
Verification Continuum III |
| March 20, 2019 | |||||
| 7:30 am - 6:00 pm | Santa Clara Convention Center |
| Registration [More Info] | ||
| 9:00 am - 10:30 am | Mission City Ballroom |
| Keynote: Shift Happens! [More Info] Speaker: Dr. Aart de Geus, Chairman & co-CEO, Synopsys | ||
| 11:00 am - 11:45 am | 212 |
| Arm Physical Design Yield Analysis with HSPICE High Sigma Monte Carlo [More Info] Speaker: Tom Mahatdejkul, Principal Design Engineer, Arm | ||
| 11:00 am - 11:45 am | Mission City 2 |
| Enabling AI with IP [More Info] Speaker: Gordon Cooper, Synopsys | ||
| 11:00 am - 11:45 am | Mission City 1 |
| Leveraging Test Fusion for Optimal PPA [More Info] Speaker: Surya Duggirala, Synopsys | ||
| 11:00 am - 11:45 am | Ballroom H |
| On Creating Reusable Stimulus Between Units and Clusters [More Info] Speaker: Krishna Gudlavalleti, Samsung Speaker: Venkat Raman, Samsung Speaker: Aparna Srinivasan, Senior Verification Engineer, Samsung | ||
| 11:00 am - 11:45 am | Great America J |
| PrimeTime 2019.03 Update [More Info] Speaker: Robert Landy, Synopsys | ||
| 11:00 am - 11:45 am | 203/204 |
| Soft Error Analysis for Functional Safety [More Info] Speaker: Fadi Maamari, Synopsys | ||
| 11:00 am - 11:45 am | Ballroom G |
| Using Simulation Acceleration to Speed Block and Platform Level IP Verification [More Info] Speaker: Devinder Gill, Synopsys | ||
| 11:00 am - 12:00 pm | Great America K |
| StarRC Product Update and Advanced Analysis/Debugging with StarRC Parasitic Explorer [More Info] Speaker: Priya Gianchandani, Synopsys Speaker: Esha Dubey, Sr CAD Design Engineer, AMD | ||
| 11:00 am - 12:30 pm | 209/210 |
| Panel: Design and Verification on the Cloud [More Info] Panelist: Preeth Chengappa, Director, Semiconductor & EDA, Azure, Microsoft Panelist: Derek Magill, Qualcomm Moderator: Sriram Sitaraman, Synopsys Panelist: Simon Burke, Xilinx Panelist: Jitendra Mohan, Astera Labs Panelist: Ramki Balasubramanian, Synopsys | ||
| 11:00 am - 12:30 pm | Hall A2 |
| Panel: Peering Beneath the Surface: A Look Inside Fusion Compiler, its Technology Underpinnings and how This Next-Generation RTL-to-GDSII Solution is Natively Architected to Deliver Class-Leading QoR and Time-to-Results [More Info] Moderator: Sanjay Bali, Synopsys Panelist: Aiqun Cao, Synopsys Panelist: Reiner Genevriere, Synopsys Panelist: Neeraj Kaul, Synopsys | ||
| 11:45 am - 12:30 pm | Ballroom G |
| Addressing Exascale Emulation Debug Complexity - The Case for a System-Level Approach [More Info] Speaker: Ribhu Mittal, Director, Program Management, Synopsys | ||
| 11:45 am - 12:30 pm | Mission City 1 |
| Advanced ATPG and Diagnostics for Emerging Nodes [More Info] Speaker: Brian Archer, Synopsys | ||
| 11:45 am - 12:30 pm | 203/204 |
| Analog Fault Simulation: A Systematic Approach to Ensuring Functional Safety and Low Defect Rate in Automotive ICs [More Info] Speaker: Tom Hsieh, Synopsys Speaker: Anand Thiruvengadam, Synopsys | ||
| 11:45 am - 12:30 pm | Mission City 2 |
| Designing AI Chips [More Info] Speaker: Tim Kogel, Synopsys Speaker: Jeffery Liao, Synopsys | ||
| 11:45 am - 12:30 pm | Ballroom H |
| Integrated Regression Convergence [More Info] Speaker: Bart Thielges, Synopsys Speaker: Meghana Chittajallu, Synopsys | ||
| 11:45 am - 12:30 pm | 212 |
| Making Sure Your Design is Robust Enough Against Variations - Efficient Monte Carlo Solution with HSPICE, FineSim and CustomSim [More Info] Speaker: Manjunatha Vadiarillat, Synopsys | ||
| 11:45 am - 12:30 pm | Great America J |
| PrimeTime Productivity Improvement: DMSA Best Practices & IMSA Roll-Up Reporting [More Info] Speaker: Jennifer Pyon, Synopsys | ||
| 12:00 pm - 12:30 pm | Great America K |
| StarRC Parameterized Spice Capability [More Info] Speaker: Jagannathan Vasudevan, Member Of Technical Staff, GLOBALFOUNDRIES | ||
| 12:30 pm - 2:00 pm | Mission City Ballroom |
| Lunch & Learn: Expanding Boundaries: Next-Generation Design-for-Test (DFT) [More Info] | ||
| 12:30 pm - 2:00 pm | Hall A1 |
| Lunch & Learn: Industry Leaders Verify with Synopsys [More Info] Panelist: Dr. Johannes Stahl, Sr. Dir., Product Marketing, Verification Group, Synopsys Panelist: Krishna Tadi, Staff Engineer, Samsung Panelist: Michael Posner, Director of Product Marketing, DesignWare USB/DisplayPort & IP Subsystem Solutions, Synopsys | ||
| 12:30 pm - 2:00 pm | Hall D |
| Networking Lunch [More Info] | ||
| 2:00 pm - 2:45 pm | No location |
| Analog Fault Simulation: A Systematic Approach to Ensuring Functional Safety and Low Defect Rate in Automotive ICs [More Info] Speaker: Tom Hsieh, Synopsys Speaker: Anand Thiruvengadam, Synopsys | ||
| 2:00 pm - 2:45 pm | Great America J |
| Beyond STA - Design Yield Analysis [More Info] Speaker: Jacob Avidan, Synopsys | ||
| 2:00 pm - 2:45 pm | Hall A3 |
| Cone by Cone Functional ECOs with Formality Ultra [More Info] Speaker: Sathappan Palaniappan, Principal Engineer, Broadcom | ||
| 2:00 pm - 2:45 pm | Ballroom H |
| Coverage Management using Adaptive Exclusions, Unreachability Analysis and Flexible Merging of Cover Groups [More Info] Speaker: Manisha Tatikonda, Director Engineering, Qualcomm Speaker: Dharmesh Mahay, Synopsys | ||
| 2:00 pm - 2:45 pm | Mission City 1 |
| DFT Shifts Left to Accelerate Time to Results! [More Info] Speaker: Adam Cron, Synopsys | ||
| 2:00 pm - 2:45 pm | 203/204 |
| Enabling Automotive - Quality Embedded Memories: Design and Test Enhancements [More Info] Speaker: Frank Cano, Distinguished Member Technical Staff, Texas Instruments | ||
| 2:00 pm - 2:45 pm | Hall A2 |
| IC Compiler II Update [More Info] Speaker: John Griner, Synopsys | ||
| 2:00 pm - 2:45 pm | Great America K |
| Improving Characterization Turnaround Time: Production Library Characterization in 24hrs [More Info] | ||
| 2:00 pm - 2:45 pm | 209/210 |
| Physical Verification on the Cloud - Solving Physical Signoff TAT Challenges [More Info] Speaker: Li-Siang Lee, Barefoot Networks Dan Page, Synopsys | ||
| 2:00 pm - 2:45 pm | Ballroom G |
| Supercharging SoC Validation [More Info] | ||
| 2:00 pm - 3:30 pm | Mission City 2 |
| Where Are We on the Road to Artificial Intelligence in Chip Design? [More Info] Speaker: Stelios Diamantidis, Synopsys Speaker: Arun Venkatachar, Synopsys Speaker: Joe Walston, Synopsys | ||
| 2:45 pm - 3:30 pm | Great America K |
| Accurate Variation Modelling Using Machine Learning [More Info] Speaker: Sucheta Harish, Qualcomm | ||
| 2:45 pm - 3:30 pm | Hall A2 |
| Adopting IC Compiler II for Chip-level Place-and-Route - A New Users Experience [More Info] Speaker: Tanvir Khan, IC Design Engineer, Broadcom | ||
| 2:45 pm - 3:30 pm | Hall A3 |
| Formality 2018.06 and 2019.03 Technology Update [More Info] Speaker: Uday Dixit, Synopsys | ||
| 2:45 pm - 3:30 pm | 212 |
| Full-chip Simulation using a Selectively Instantiated Netlist with Array Model Integration [More Info] Speaker: Brandon Low, Senior Verification Engineer, Nantero | ||
| 2:45 pm - 3:30 pm | Mission City 1 |
| Low-Cost X-Tolerant LBIST Solution for Automotive IC [More Info] | ||
| 2:45 pm - 3:30 pm | 209/210 |
| Modernizing Workloads on the Cloud [More Info] Speaker: Ramki Balasubramanian, Synopsys Speaker: Jaimin Desai, Synopsys Speaker: Melvin Cardozo, Synopsys | ||
| 2:45 pm - 3:30 pm | Great America J |
| Next Generation of Simultaneous Multi Voltage Analysis [More Info] | ||
| 2:45 pm - 3:30 pm | Ballroom H |
| Reusable Verification IP for Control Path Stress Testing [More Info] Speaker: Rakesh Vummaneni, Senior Engineer, Samsung | ||
| 2:45 pm - 3:30 pm | Ballroom G |
| Rigorous Access Control Testing with Hardware Emulation [More Info] Speaker: Jean-Philippe Martin, Security Consultant, Start With WCPGW | ||
| 2:45 pm - 3:30 pm | 203/204 |
| The Marriage of AI and Safety in Automotive SoCs [More Info] Speaker: Fergus Casey, Synopsys | ||
| 3:45 pm - 4:15 pm | Hall A2 |
| Critical Path Timing Optimization and Feedback Method in Design Planning using Preroutes, Repeaters and User Tables [More Info] | ||
| 3:45 pm - 4:15 pm | Mission City 1 |
| Improve DFT Implementation with SpyGlass DFT ADV in RTL Sign-off [More Info] Speaker: Ruoyu Liu, Broadcom | ||
| 3:45 pm - 4:30 pm | Ballroom H |
| Achieving Predictable Functional and Performance Verification Closure of Complex Interconnect Subsystems [More Info] Speaker: Bernie DeLay, Synopsys | ||
| 3:45 pm - 4:30 pm | Great America K |
| Easier and Faster NanoTime Configuration for Timing Analysis of SRAMs and Other Macros [More Info] Speaker: Ketan Zaveri, Synopsys | ||
| 3:45 pm - 4:30 pm | 212 |
| Electromigration Analysis Flow using Synopsys CustomSim Reliability Analysis for GlobalFoundries’ 22FDX Technology [More Info] Speaker: Amit Kumar, EMIR for CustomSim-RA, GLOBALFOUNDRIES | ||
| 3:45 pm - 4:30 pm | Great America J |
| Machine Learning Accelerated ECO and Latest Advances with PrimeTime-ADVPlus [More Info] Speaker: Troy Epperly, Synopsys | ||
| 3:45 pm - 4:30 pm | Hall A3 |
| Using Fusion Compiler to Improve QoR/Runtime [More Info] Speaker: Vishal Jain, Qualcomm | ||
| 3:45 pm - 4:30 pm | Mission City 2 |
| Using Machine Learning for Characterization of NoC Components [More Info] Speaker: Benny Winefeld, Solutions Architect, ArterisIP | ||
| 3:45 pm - 4:30 pm | 203/204 |
| Virtual Hardware ECUs: A Positive Disruption for Automotive Software Development [More Info] Speaker: Charu Khosla, Synopsys | ||
| 3:45 pm - 5:15 pm | Ballroom G |
| Billion-Cycle Power Estimation using Fast Emulation [More Info] Speaker: Alex Wakefield, Synopsys | ||
| 3:45 pm - 5:15 pm | Mission City Ballroom |
| Women in Semiconductors: Designing Your Future [More Info] Moderator: Deirdre Hanford, co-General Manager Design Group, Corporate Staff, Synopsys Panelist: Mulan Li, Director of Physical Design Engineering, NVIDIA Panelist: Penny Li, SambaNova Systems Panelist: Latha Venkatachari, VP, Applications Engineering, Synopsys Panelist: Sundari Mitra, Vice President, Silicon Engineering Group & General Manager, Configurable IP and Chassis Group, Intel Diane Bryant, Keynote | ||
| 4:15 pm - 4:45 pm | Hall A2 |
| Hierarchical Design Planning Challenges for Large Complex Sub-Chips [More Info] Speaker: Semmal Ganapathy, NVIDIA | ||
| 4:15 pm - 4:45 pm | Mission City 1 |
| Lightweight LBIST Implementation Methodology for Small Cores [More Info] Speaker: Ingoo Jung, Principal Digital Designer, Renesas | ||
| 4:30 pm - 5:15 pm | 203/204 |
| An Emulation Based Fault Injection Platform for Functional Safety Verification [More Info] | ||
| 4:30 pm - 5:15 pm | Ballroom H |
| Automating Verdi-based Simulation Debug using Perl/Python [More Info] Speaker: Omar Azzam, NVIDIA | ||
| 4:30 pm - 5:15 pm | Mission City 2 |
| Building Machine Learning-enabled Chip Design Flows [More Info] Speaker: Smarahara Misra, Synopsys Speaker: Sashi Obilisetty, Synopsys | ||
| 4:30 pm - 5:15 pm | 212 |
| Crosstalk Analysis on Custom Ciruits using Advanced CustomSim Circuit Check [More Info] Speaker: Raed Sabbah, Cad Engineer, Micron Technology | ||
| 4:30 pm - 5:15 pm | Great America K |
| QoR Analysis Using Aging-enabled Liberty Variation Format (LVF) Design Flow for Automotive and IoT High Reliability Applications [More Info] Speaker: Siddharth Sawant, Member of Technical Staff, GLOBALFOUNDRIES | ||
| 4:45 pm - 5:15 pm | Hall A2 |
| Power Optimization Techniques In Advanced Nodes for Networking ASICs [More Info] Speaker: Vivek Pagadala, Juniper Networks Speaker: Naman Sharma, Juniper Networks | ||
| 4:45 pm - 5:15 pm | Mission City 1 |
| Test and Repair for SoC Memories and Hierarchical Test for AMS & PHY IP [More Info] Speaker: Yervant Zorian, Synopsys | ||
| 5:15 pm - 7:00 pm | Hall B |
| SNUG Pub [More Info] | ||
| March 21, 2019 | |||||
| 8:00 am - 5:15 pm | Santa Clara Convention Center |
| Registration [More Info] | ||
| 9:15 am - 10:15 am | Mission City Ballroom |
| Keynote: Applications of Unsupervised Learning [More Info] Speaker: Bryan Catanzaro, VP of Applied Deep Learning Research, NVIDIA | ||
| 10:45 am - 11:15 am | Hall A2 |
| Drive Faster Signoff Closure and Eliminate ECO Iterations with ECO Fusion [More Info] Speaker: Farokh Yazdani, Synopsys | ||
| 10:45 am - 11:30 am | Ballroom G |
| A Gentle Introduction to Formal Verification [More Info] Speaker: Subramani Ganesh, Principal ASIC Engineer, Palo Alto Networks | ||
| 10:45 am - 11:30 am | Ballroom H |
| A Novel Methodology for Comprehensive Glitch Detection [More Info] Speaker: Mohd Imran Beg, Samsung | ||
| 10:45 am - 11:30 am | Mission City 1 |
| Accelerating Debug of Assertions by Leveraging Synopsys HAPS Prototyping with Verdi [More Info] Speaker: Sriram Manjunath, Sr Asic Design Engineer, NVIDIA | ||
| 10:45 am - 11:30 am | 212 |
| Boost of Mismatch Simulations in HSPICE using Mirror Options [More Info] Speaker: Jie Min, Sr. Engineer, Design Enablement, GLOBALFOUNDRIES | ||
| 10:45 am - 11:30 am | 209/210 |
| Building Secure Media Processors for Connected Homes using OTP NVM [More Info] Speaker: Jingliang Li, ASIC Design Engineer, Synaptics | ||
| 10:45 am - 11:30 am | Mission City 2 |
| Moving AI to the Edge with Synopsys ASIP Designer [More Info] Speaker: Drew Taussig, Synopsys | ||
| 10:45 am - 11:30 am | Great America J |
| SoC Early Power Estimation Challenges and Accuracy: How To Get It Done Right [More Info] Speaker: Sourabh Vaid, IC Design Engineer, Broadcom | ||
| 10:45 am - 12:15 pm | Hall A3 |
| Design Compiler® NXT and Power Compiler - Tutorial Covering Latest Release Updates [More Info] Speaker: Bob Wiegand, Synopsys Speaker: Abhijeet Chakraborty, Synopsys | ||
| 11:15 am - 11:45 am | Hall A2 |
| Accelerating EMIR Closure with RedHawk Analysis Fusion [More Info] Speaker: Krishnaraj Rajan, Synopsys | ||
| 11:30 am - 12:15 pm | 209/210 |
| Enabling 400G Hyperscale Data Centers with 56G Ethernet PHY IP [More Info] Speaker: Rita Horner, Synopsys | ||
| 11:30 am - 12:15 pm | Ballroom G |
| Formal Regressions - Resource Hungry Waste or High Value Results? [More Info] Speaker: Iain Singleton, Synopsys | ||
| 11:30 am - 12:15 pm | Mission City 1 |
| FPGA Prototyping for Consumer and Enterprise SSD Devices [More Info] Speaker: Chun Hok Ho, Senior Manager, SK Hynix | ||
| 11:30 am - 12:15 pm | 212 |
| Performance Optimization of Transient Noise Analysis with FineSim SPICE [More Info] Speaker: Youngjae Park, Senior Engineer, Samsung | ||
| 11:30 am - 12:15 pm | Great America J |
| PTPX to PrimePower - Power User's Journey [More Info] Speaker: Anand Iyer, Senior Design Engineer, Microsoft | ||
| 11:30 am - 12:15 pm | Ballroom H |
| STA Compatible Netlist Level Clock Domain Crossing Validation [More Info] Speaker: Tanveer Singh, Synopsys | ||
| 11:30 am - 12:15 pm | Mission City 2 |
| Verdi Machine Learning Case Study: Regression Failure Root Cause Automation [More Info] Speaker: Kent Yang, Synopsys | ||
| 11:45 am - 12:15 pm | Hall A2 |
| IC Compiler II-RedHawk-SC Fusion Flow Based IR Aware Placement [More Info] Speaker: Shankarshana Janarthanan, NVIDIA | ||
| 12:00 pm - 1:30 pm | Hall D |
| Networking Lunch [More Info] | ||
| 12:15 pm - 1:45 pm | Hall A1 |
| Lunch & Learn: Realizing Best-in-Class QoR and the Fastest Time-to-Market with the Synopsys Fusion Design Platform [More Info] | ||
| 12:15 pm - 1:45 pm | Mission City Ballroom |
| Lunch & Learn: Synopsys Custom Design Platform: Accelerating Robust Custom Design [More Info] Tom Mahatdejkul, Principal Design Engineer, Arm Ashish Kumar, Sr. Manager / Member of Technical Staff, STMicroelectronics Soonkeol Ryu, Principal Engineer of Design Technology Team, Samsung Foundry Bob Lefferts, Director of World-Wide CAD, Solutions Group, Synopsys | ||
| 1:45 pm - 2:15 pm | Hall A2 |
| Extending QoR Differentiation on GF 12LP with Synopsys' Advanced Fusion Technologies [More Info] Speaker: Pratik Rajput, MTS Design Engineer, GLOBALFOUNDRIES | ||
| 1:45 pm - 2:30 pm | Great America J |
| Accelerating Design Signoff with Software-driven Power Analysis [More Info] Speaker: Kanishka De, Synopsys | ||
| 1:45 pm - 2:30 pm | 212 |
| Accelerating Simulation of High Accuracy Analog Designs with FineSim [More Info] Speaker: Gim Tan, Synopsys | ||
| 1:45 pm - 2:30 pm | Hall A3 |
| Hierarchical Design Flow with Full-Depth Verification using Synthesis and Place & Route Tool Abstraction Features [More Info] | ||
| 1:45 pm - 2:30 pm | Mission City 2 |
| Leveraging ML to Improve VC LP Root Cause Analysis [More Info] Speaker: Himanshu Bhatt, Synopsys | ||
| 1:45 pm - 2:30 pm | Ballroom G |
| Scalable & Reusable Reset Connectivity Flow: A Formal Approach [More Info] Speaker: Srikanth Vadanaparthi, Staff Engineer, Qualcomm | ||
| 1:45 pm - 2:30 pm | 209/210 |
| Using IP for LPDDR5/4/4X Connectivity and Memory Performance Optimization [More Info] Speaker: Graham Allan, Synopsys | ||
| 1:45 pm - 3:15 pm | Ballroom H |
| Systematic Low Power Verification for Early Detection of Power Intent Bugs [More Info] Speaker: Chetan Avlani, Masters Engineer, Broadcom | ||
| 2:15 pm - 2:45 pm | Hall A2 |
| Onwards and Upwards: How Xilinx is Leveraging TSMCs Latest Integration-and-Packaging Technologies with Synopsys Platform-wide Implementation Solution for our Next Generation Designs [More Info] Speaker: Simon Burke, Xilinx | ||
| 2:30 pm - 3:15 pm | 209/210 |
| Combining Monocular Visual SLAM and Deep Learning Low-Power Embedded Vision Systems for Augmented Reality [More Info] Speaker: Gordon Cooper, Synopsys | ||
| 2:30 pm - 3:15 pm | Hall A3 |
| Finite State Machine I (FSM) Design & Synthesis using SystemVerilog [More Info] Speaker: Cliff Cummings, Sunburst Design Speaker: Heath Chambers, President / Verification Designer, HMC Design Verification | ||
| 2:30 pm - 3:15 pm | Mission City 2 |
| High Performance Formal Verification: A Perfect Use of Machine Learning Techniques [More Info] Speaker: Himanshu Jain, Synopsys Speaker: Dmitry Burlyaev, Synopsys | ||
| 2:30 pm - 3:15 pm | 212 |
| Laker to Custom Compiler: A Journey [More Info] Speaker: Sarvesh Ganesan, Microsoft | ||
| 2:30 pm - 3:15 pm | Ballroom G |
| More than Just Connectivity Check: Visibility, Capacity, Performance, Debug, Connectivity Extraction, and Closure [More Info] Speaker: Sneha Patel, Broadcom | ||
| 2:30 pm - 3:15 pm | Great America J |
| No Vectors? No Problem! Analyzing Power Earlier with PrimePower 2019 [More Info] Speaker: Mahmud Ullah, Synopsys | ||
| 2:30 pm - 3:15 pm | Ballroom H |
| UPF Information Model: Key to Efficient Power Aware Verification [More Info] Speaker: Sriram Hariharan, Principal Engineer/Manager, Qualcomm | ||
| 2:45 pm - 3:15 pm | Hall A2 |
| Block Level CTS Debug With IC Compiler II [More Info] Speaker: Pete Churchill, Synopsys | ||
| 3:30 pm - 4:15 pm | Ballroom G |
| 5G Mobile SoC Pre-RTL Power/Performance Optimization [More Info] | ||
| 3:30 pm - 4:15 pm | 209/210 |
| Accelerate Your Move to 32GT/s PCI Express 5.0 Designs [More Info] Speaker: Gary Ruggles, Synopsys | ||
| 3:30 pm - 4:15 pm | Ballroom H |
| Am I Implementing What I Have Simulated? [More Info] Speaker: Mahiro Hikita, Socionext | ||
| 3:30 pm - 4:15 pm | Hall A2 |
| Full Flow Physical Verification Productivity using IC Validator [More Info] Speaker: Dan Page, Synopsys Speaker: Nobuhiko Ogawa, Chief Specialist, Design Technology Development, Toshiba Speaker: Chris Grossmann, Synopsys | ||
| 3:30 pm - 4:15 pm | 212 |
| High Speed SerDes - What are the Challenges for Advanced Nodes? [More Info] Speaker: Ayal Shoval, Member of Technical Staff, Synopsys | ||
| 3:30 pm - 5:00 pm | Hall A3 |
| Best Practices using Synopsys Fusion Technology to Achieve High-performance, Energy Efficient implementations of the latest Arm® Processors in 7-nanometer FinFET (7FF) Process Technology [More Info] Speaker: Mike Montana, Synopsys Speaker: Leah Schuth, Arm | ||
| 3:30 pm - 5:00 pm | Mission City 2 |
| Panel: How is AI Transforming Chip Design and Verification? [More Info] Moderator: Chekib Akrout, Synopsys Panelist: Alan Lee, AMD Panelist: Dhiraj Mallick, Cerebras Systems Panelist: Keith Witek, SiFive Panelist: Yankin Tanurhan, Synopsys | ||
| 4:15 pm - 5:00 pm | 212 |
| Analog Design Closure [More Info] Speaker: Karun Sharma, Synopsys | ||
| 4:15 pm - 5:00 pm | Ballroom H |
| Early UPF Checking and Hierarchical Low Power Static Verification [More Info] Speaker: Himanshu Bhatt, Synopsys Speaker: Nishant Patel, Senior Applications Engineer, Synopsys | ||
| 4:15 pm - 5:00 pm | Ballroom G |
| End-to-End Software Development and Testing using Virtual Prototyping with Virtualized PCIe I/O [More Info] Speaker: Mojin Kottarathil, Synopsys | ||
| 4:15 pm - 5:00 pm | Hall A2 |
| Pushing the Limit: Improvement of Design Routability in the EUV Technology [More Info] Speaker: Jun Seomun, Samsung | ||
| 5:00 pm - 6:30 pm | Hall B |
| Awards and SNUG After Party [More Info] | ||
| row-start row-end col-md-12 sponsorlogos-section center |
