| 9:00 am - 9:45 am | Alma Lobby Restaurant | | Registration and Breakfast [More Info] |
| 9:45 am - 10:30 am | Venus & Afrodita | | Synopsys Keynote - High Impact Innovation [More Info]
Speaker: Sassine Ghazi, co-General Manager Design Group, Corporate Staff, Synopsys
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| 10:30 am - 11:30 am | Venus & Afrodita | | Design & Verification on the Cloud [More Info]
Moderator: Sriram Sitaraman, Synopsys
Speaker: Jacob Avidan, Synopsys
Panelist: Yair Armoza, Amazon
Panelist: Noam Brousard, ProteanTecs
Panelist: Dror Reznik, RamonChips
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| 11:30 am - 11:50 am | Alma Lobby Restaurant | | Break [More Info] |
| 11:50 am - 12:50 pm | Pacific (Sub-Level 1) | | Introduction to Next-gen Static Verification Solution for RTL Signoff [More Info]
Speaker: Kaushik De, Synopsys
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| 11:50 am - 12:50 pm | Poseidon | | The DNA of Intelligent SoCs [More Info]
Speaker: John Koeter, Synopsys
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| 11:50 am - 12:50 pm | Danieli Theater | | Verification Challenges and Solutions in Emerging Market Segments [More Info]
Speaker: Eshel Haritan, Synopsys
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| 11:50 am - 1:20 pm | Venus & Afrodita | | Fusion Compiler and Custom Compiler: Digital (RTL-to-GDSII) and Custom Design Implementation [More Info]
Speaker: Frank De Meersman, Synopsys
Speaker: Aveek Sarkar, Synopsys
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| 12:50 pm - 1:45 pm | Hemmingway Restaurant | | Verification & IP Networking Lunch [More Info] |
| 1:20 pm - 2:15 pm | Hemmingway Restaurant | | Implementation Networking Lunch [More Info] |
| 1:45 pm - 2:15 pm | Poseidon | | Accelerating the Path to a Safe and Secure SoC [More Info]
Speaker: Yankin Tanurhan, Synopsys
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| 1:45 pm - 2:15 pm | Pacific (Sub-Level 1) | | Software-Driven Power Estimation with ZeBu Emulator [More Info]
Speaker: Idan Berko, Synopsys
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| 1:45 pm - 2:30 pm | Atlantic (Sub-Level 1) | | Mastering Artificial Intelligence System Architecture [More Info]
Speaker: Ohad Amrami, Synopsys
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| 1:45 pm - 2:45 pm | Danieli Theater | | Functional Safety for Automotive Introduction [More Info]
Speaker: Joerg Richter, Synopsys
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| 2:15 pm - 2:45 pm | Poseidon | | Advanced Vector Floating Point DSP Processing for Automotive Applications [More Info]
Speaker: Yankin Tanurhan, Synopsys
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| 2:15 pm - 2:45 pm | Typhoon (Sub-level 1) | | Early RC Analysis with Custom Compiler Visually-Assisted Automation and Fusion Technologies [More Info]
Speaker: Uri Golan, Synopsys
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| 2:15 pm - 2:45 pm | Afrodita | | R&D Vision Session: Beyond STA - Design Yield Analysis [More Info]
Speaker: Jacob Avidan, Synopsys
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| 2:15 pm - 2:45 pm | Pacific (Sub-Level 1) | | System Verilog Assertions on Emulation An Effective Bug Finder [More Info] |
| 2:15 pm - 2:45 pm | Venus | | World Record Transistor Count Achieved using Synopsys Customized Placement Flow [More Info]
Speaker: Shy Mosseri, Broadcom
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| 2:30 pm - 3:15 pm | Atlantic (Sub-Level 1) | | Virtual Hardware ECUs: A Positive Disruption for Automotive Software Development [More Info]
Speaker: Hila Balahsan, Synopsys
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| 2:45 pm - 3:15 pm | Poseidon | | Advanced Uniformed Test Approach for Automotive SOCs [More Info] |
| 2:45 pm - 3:15 pm | Danieli Theater | | Enhanced Testbech Configuration Object Structure for Smooth on-the-fly Re-randomization [More Info] |
| 2:45 pm - 3:15 pm | Pacific (Sub-Level 1) | | Getting the Most out of your Emulation Budget [More Info] |
| 2:45 pm - 3:15 pm | Venus | | IC Compiler II Update [More Info]
Speaker: Leonid Rabinovich, Synopsys
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| 2:45 pm - 3:15 pm | Afrodita | | Machine Learning Usage During Power Optimization [More Info] |
| 2:45 pm - 3:15 pm | Typhoon (Sub-level 1) | | ProteanTecs Custom Design Flow for Advanced Technology Nodes [More Info]
Speaker: Alla Svidler, ProteanTecs
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| 3:15 pm - 3:30 pm | Alma Lobby Restaurant | | Break [More Info] |
| 3:30 pm - 4:00 pm | Typhoon (Sub-level 1) | | Analog Fault Simulation [More Info]
Speaker: Alon Sasson, Synopsys
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| 3:30 pm - 4:00 pm | Atlantic (Sub-Level 1) | | Bottom-up Methodology for Full-Chip Clock Domain Crossings (CDC) Verification [More Info]
Speaker: Asaf Kizerman, Avnet
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| 3:30 pm - 4:00 pm | Poseidon | | Enabling New 400G+ Network Architectures with 56G Ethernet PHY IP [More Info]
Speaker: Michael Chen, Synopsys
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| 3:30 pm - 4:00 pm | Afrodita | | Next Generation of Simultaneous Multi Voltage Analysis [More Info] |
| 3:30 pm - 4:00 pm | Venus | | RTL Synthesis for Next Decade with Design Compiler NXT [More Info]
Speaker: Israel Gur-Arie, Synopsys
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| 3:30 pm - 4:00 pm | Danieli Theater | | Testbench Qualification Metrics by Inducing Faults to HLS Design [More Info] |
| 3:30 pm - 4:00 pm | Pacific (Sub-Level 1) | | Verdi HWSW FW Development with RTL Simulation [More Info]
Speaker: Eli Ben-Shimol, Valens
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| 4:00 pm - 4:30 pm | Typhoon (Sub-level 1) | | Accelerating Simulation of High Accuracy Analog Designs with FineSim [More Info]
Speaker: David Shaya, Synopsys
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| 4:00 pm - 4:30 pm | Venus | | Flow for Automatic Silicon Interposer Design of HBM-based Applications [More Info]
Speaker: Uri Golan, Synopsys
Speaker: Leonid Rabinovich, Synopsys
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| 4:00 pm - 4:30 pm | Afrodita | | IC Validator: Full Flow Physical Verification Productivity [More Info]
Speaker: Hitesh Patel, Synopsys
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| 4:00 pm - 4:30 pm | Pacific (Sub-Level 1) | | Making your FPGA Clear as Glass [More Info]
Speaker: Lior Grinzaig, Corning
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| 4:00 pm - 4:30 pm | Poseidon | | Reducing Dynamic Power and Time-to-Tapeout for High-Performance AI Processor SoCs [More Info]
Speaker: Yudhan Rajoo, Synopsys
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| 4:00 pm - 4:30 pm | Danieli Theater | | Three Clever Ways to use EDA Tools in Post Silicon Debug [More Info] |
| 4:00 pm - 4:30 pm | Atlantic (Sub-Level 1) | | Timing Analysis of Unconstrained Clock Domain Crossings the Need and the Method [More Info] |
| 4:30 pm - 5:00 pm | Venus Hall | | Best Paper Award and Prize Drawing [More Info] |
