SNUG Austin 2018

Tuesday, October 23, 2018

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AMS Frontend Implementation
Frontend/Physical Implementation General Sessions
Machine Learning Physical Implementation
Test User Content Reviewed by the Technical Committee
Verification Continuum I Verification Continuum II (Emulation/Prototyping)
Verification Continuum III 

Tuesday, October 23, 2018
9:00 am - 10:45 amGovernor’s Ballroom
Keynote - At the Heart of Impact (Aart de Geus) [More Info]
Dr. Aart de Geus, Chairman & co-CEO, Synopsys
11:00 am - 11:30 am410
What's New in Emulation [More Info]
Dr. Johannes Stahl, Director, Product Marketing, Virtual Prototyping, Synopsys
11:00 am - 11:45 am408
Optimizing Reliability Verification Analysis on Large Scale Memory and Mixed Signal Designs [More Info]
11:00 am - 11:45 am406
Use the Sequence, Luke: Guidelines to Reach the Full Potential of UVM Sequences [More Info]
Jeffrey Montesano, Senior Verification Consultant, Verilab
Jeff Vance, Design Verification Engineer, Verilab
11:00 am - 12:00 pmSalon D/E
High-Performance Arm®-based CPU Implementation for Mobile Devices [More Info]
Brian Millar, Samsung
11:00 am - 12:30 pm412
Automotive Test Requirements Drives Test Automation Features [More Info]
Adam Cron, Synopsys
11:30 am - 12:00 pm410
Getting Started on Co-Emulation: Primer on Why and How to Transition Your Design and UVM Testbench to an Emulator [More Info]
Jigar Savla, Engineer, Juniper Networks
11:45 am - 12:30 pm408
Analog Fault Simulation [More Info]
Anand Thiruvengadam, Senior Product Marketing Manager, Synopsys
11:45 am - 12:30 pm406
Error Injection in a Subsystem Level Constrained Random UVM Testbench [More Info]
Jeremy Ridgeway, Principal Verification Engineer, Broadcom
12:00 pm - 12:30 pm410
Early Security Intent Verification with ZeBu [More Info]
Jean-Philippe Martin, Security Consultant, Start With WCPGW
12:00 pm - 12:30 pmSalon D/E
Improving PPA with New Fusion Technologies [More Info]
Subbu Yarlagadda, Synopsys
12:30 pm - 1:45 pmGovernor’s Ballroom
Networking Lunch [More Info]
1:45 pm - 2:05 pm412
SpyGlass DFT ADV Early Testability Analysis and Physically-Aware Test Point Insertion [More Info]
Brad MacMonagle, Senior Staff Application Consultant, Synopsys
1:45 pm - 2:25 pmSalon E
Best Practices and Synopsys QuickStart Implementation Kits (QIKs) for the Latest Armv8-A Processors [More Info]
Mike Montana, Synopsys
Lisa Minwell, Sr. IP Solutions Marketing Manager, Arm
1:45 pm - 2:25 pm410
Emulation Efficiency Improvements [More Info]
1:45 pm - 2:25 pmSalon D
Power Savings Toolbox for High Speed Designs [More Info]
1:45 pm - 2:25 pm408
Synopsys PowerReplay for Earlier & Faster Power Analysis [More Info]
Al Benavides, Synopsys
1:45 pm - 2:25 pm406
VC Formal Apps Expansion: Security and X-Prop [More Info]
Tareq Altakrouri, Synopsys
Anders Nordstrom, Synopsys
2:05 pm - 2:15 pm412
Using SpyGlass DFT ADV Physically-Aware Test Points to Improve TetraMAX ATPG QoR and Minimize Layout Issues [More Info]
Shwetha Shivashankar Murthy, Qualcomm
2:15 pm - 2:45 pm412
Stuck-At Test Coverage Improvement for the Qualcomm Hexagon DSP using Z01X [More Info]
Preston McWithey, Staff Engineer, Qualcomm
Paul Policke, Principal Engineer/Manager, Qualcomm
2:25 pm - 3:05 pm406
Enhancing Verification Quality of Very High Radix Divider Designs by using Formal Tools [More Info]
Pratyush Jain, Senior Design Engineer, Advanced Micro Devices
2:25 pm - 3:05 pmSalon D
Faster Timing Closure and Power Saving for VPU (Vision Processing Unit) SoC Intended for Deep Learning and AI Acceleration [More Info]
2:25 pm - 3:05 pm410
Regression Testing for Verification of Advanced CPU Subsystems using Fast Emulation [More Info]
Eric White, Senior Member of Technical Staff, Cores Verification and Emulation, Advanced Micro Devices
Syed Obaidulla, Senior Member of Technical Staff, Technical Lead DFT Verification & Emulation, Advanced Micro Devices
2:25 pm - 3:05 pm408
UVM Analysis Port Functionality and Using Transaction Copy Commands [More Info]
Heath Chambers, President / Verification Designer, HMC Design Verification
Cliff Cummings, Sunburst Design
2:25 pm - 3:05 pmSalon E
What's New with IC Compiler II [More Info]
James Harper, Synopsys
2:45 pm - 3:15 pm412
Improvements in ATPG and DRC Runtimes for Large SoCs with TetraMAX II [More Info]
Jonathon E. Colburn, NVIDIA
3:05 pm - 3:45 pmSalon D
Accelerating Full Chip Timing Closure in Pre-ECO and ECO Phases [More Info]
Lovish Masand, Sr. ASIC/Layout Design Engineer, Advanced Micro Devices
3:05 pm - 3:45 pmSalon E
Block Level Floorplan Debug With IC Compiler II [More Info]
Pete Churchill, Synopsys
3:05 pm - 3:45 pm406
Formal Property Checking Applied to Low-Power Microcontroller Designs [More Info]
Nemo Zhong, Verification Engineer, NXP
3:05 pm - 3:45 pm408
Managing Highly Configurable Design and Verification [More Info]
Jeremy Ridgeway, Principal Verification Engineer, Broadcom
3:05 pm - 3:45 pm410
SimXL Tutorial [More Info]
Hillel Miller, Synopsys
Wei-Hua Han, Synopsys
3:15 pm - 3:45 pm412
High Speed Input Output (HSIO) Test Automation and Standardization Using the Origen-SDK Open Source Platform [More Info]
Shane Sanders, Principal Member of Technical Staff, Advanced Micro Devices
4:00 pm - 4:30 pm410
Out-of-the-Box Prototyping Enabling Interactive Software Development [More Info]
Carl Cleaver, Synopsys
Bob Efram, Synopsys
4:00 pm - 4:45 pmSalon D
Design Compiler Graphical Update and Advanced Node Support [More Info]
Jim Argraves, Synopsys
4:00 pm - 4:45 pmSalon E
PG Network Creation and Analysis for Advanced Node Designs [More Info]
Xiang Qiu, Synopsys
4:00 pm - 4:45 pm406
Proving the Capability of Arm® IP for Functional Safety Applications [More Info]
Asif Jafri, Arm
4:00 pm - 5:30 pm408
Solving Reset Domain Crossings Using VC SpyGlass RDC [More Info]
Deep Shah, Synopsys
Jay Dutt, Synopsys
Muralee Ramakrishnan, Cirrus Logic
4:00 pm - 5:30 pm412
Synopsys Machine Learning [More Info]
Joe Walston, Synopsys
4:30 pm - 5:00 pm410
Driving Performance and Power Tuning Pre-silicon [More Info]
Andrew Ross, Advanced Micro Devices
4:45 pm - 5:30 pm406
Diagnostic Coverage and ASIL Rating A Z01X based LPDDR4 IP Case Study [More Info]
Shivakumar Chonnad, Sr Staff Design Engineer (IP Quality and Functional Safety), Synopsys
Sukaniyaa G Menon, Application Engineer II, Synopsys
4:45 pm - 5:30 pmSalon E
Fast, High-Quality Interconnect Pre-Routing with IC Compiler II [More Info]
Dan Guilin, Engineering Director, Synopsys
4:45 pm - 5:30 pmSalon D
Formality Best Practices and Technology Update [More Info]
Steve Lamb, Synopsys
5:00 pm - 5:30 pm410
Emulation Methodology [More Info]
Amol Bhinge, NXP
5:30 pm - 7:00 pmGovernor’s Ballroom
SNUG Pub & Awards [More Info]
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