| 8:00 am - 9:00 am | Ballroom 4 Foyer | | Registration/Breakfast [More Info] |
| 9:00 am - 9:15 am | Ballroom 4 | | Welcome [More Info] |
| 9:15 am - 10:15 am | Ballroom 4 | | Keynote -"The Future of Mobility Autonomous Vehicles" [More Info]
Chua Chee Seong, President & Managing Director, Infineon Technologies Asia Pacific Pte Ltd
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| 10:20 am - 10:45 am | Ballroom 4 | | A Novel Approach in Security Implementation and Clock Tree Synthesis using IC Compiler II [More Info]
Samuel Jigme Harrison, STM
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| 10:20 am - 10:45 am | Function Room 6 | | Dynamic Power Recovery through Clock Tree Optimization [More Info] |
| 10:20 am - 10:45 am | Ballroom 2 | | Maximizing Testbench Reusability by Adapting Pre-compile IP Methodology [More Info] |
| 10:20 am - 10:45 am | Function Room 7 | | Multi-Voltage Design Floorplanning with Black-Box Netlists & Stub UPFs [More Info] |
| 10:45 am - 11:25 am | Function Room 7 | | Accelerate Time-to-Market with RedHawk Analysis Fusion and Maximize Design Robustness [More Info]
Bryan Chen, Synopsys
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| 10:45 am - 11:25 am | Ballroom 4 | | IC Compiler II Technology Update [More Info]
Arvind Narayanan, Synopsys
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| 10:45 am - 11:25 am | Function Room 6 | | Signoff Power Analysis Driven PrimeTime ECO for Best PPA - Accelerated by Machine Learning [More Info]
Vivek Ghante, Synopsys
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| 10:45 am - 11:25 am | Ballroom 2 | | Whats New in Emulation and Why: Technology Trends and Drivers in Emulation [More Info]
Sivaprasad Acharaya, Synopsys
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| 11:25 am - 11:50 am | Function Room 7 | | Channel Partition Global Clock Implementation [More Info] |
| 11:25 am - 11:50 am | Function Room 6 | | Efficient Static Timing Analysis for Accurate Programmable Logic Performance [More Info] |
| 11:25 am - 11:50 am | Ballroom 4 | | High Performance Design Optimization Technique Via Guided Useful Skew [More Info] |
| 11:25 am - 11:50 am | Ballroom 2 | | Targeted Formal Verification to Improve Efficiency and Close Coverage Gaps in SoC Verification [More Info] |
| 11:50 am - 1:00 pm | Ballroom 3 | | Networking Lunch [More Info] |
| 1:00 pm - 1:10 pm | Ballroom 4 | | Welcome Back [More Info] |
| 1:10 pm - 2:10 pm | Ballroom 4 | | Vision Address - The Pace of Innovation [More Info]
Don Chan, Senior Vice President, Design Group, Synopsys
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| 2:15 pm - 2:55 pm | Ballroom 4 | | Achieving Best QOR and Fastest Time to Results with Synopsys' Fusion Platform [More Info]
Arvind Narayanan, Synopsys
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| 2:15 pm - 2:55 pm | Function Room 7 | | AI Chip Design from the Data-Center to the Edge [More Info]
Swee Guan, Synopsys
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| 2:15 pm - 2:55 pm | Function Room 6 | | PrimeTime Reporting Runtime & Productivity Improvements [More Info]
Vivek Ghante, Synopsys
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| 2:15 pm - 2:55 pm | Ballroom 2 | | Tackling SystemVerilog and UVM Testbench Debug Challenges Interactive Debug with Verdi and VCS [More Info]
Eugene Ho, Synopsys
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| 2:55 pm - 3:20 pm | Function Room 6 | | A Systematic and Accurate Methodology for Complex Programmable Logic Interconnect Performance [More Info] |
| 2:55 pm - 3:20 pm | Ballroom 4 | | CCD Technology Highlight/Customer (Renesas) Success Experience Sharing [More Info]
Anusha Reddy Sindhwala, Synopsys
Phuoc Le Ngoc Vu, Renesas
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| 2:55 pm - 3:20 pm | Ballroom 2 | | Improved Productivity in Functional Coverage Closure with VCSMX ECHO Technology [More Info]
Thanh Tran, Renesas
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| 2:55 pm - 3:20 pm | Function Room 7 | | Physical-aware Timing Budgeting in SoC Design [More Info] |
| 3:20 pm - 3:50 pm | Ballroom 4 Foyer | | Tea Break [More Info] |
| 3:55 pm - 4:20 pm | Ballroom 4 | | A Holistic Methodology of Zero-cycle Timing Path for Latency Reduction [More Info]
Simin Xu, Xilinx
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| 3:55 pm - 4:20 pm | Function Room 7 | | A Practical Library Qualification Methodology with Interconnect Parasitic Consideration in an Automated Correlation Test Case [More Info]
Lain Shen Tyah, eAsic
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| 3:55 pm - 4:20 pm | Function Room 6 | | Best Practices in Synthesis Area Recovery Using optimize_netlist [More Info]
Chin Leong Lou, ChipGlobe
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| 3:55 pm - 4:20 pm | Ballroom 2 | | IP Level CDC Abstract Verification Process for Efficient CDC Analysis at SoC Level [More Info] |
| 4:20 pm - 5:00 pm | Ballroom 4 | | Achieve Faster Design Closure Utilizing IC Compiler II Placement and Optimization Technologies [More Info]
Anusha Reddy Sindhwala, Synopsys
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| 4:20 pm - 5:00 pm | Ballroom 2 | | Comprehensive SDC-based Clock Domain Crossing Verification [More Info]
Ajay Rana, Synopsys
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| 4:20 pm - 5:00 pm | Function Room 6 | | Design Compiler Recent Technology Enhancements, QoR Improvements & Roadmap/Customer Success Experience Sharing [More Info]
Hari Narayan Shanmugam, Synopsys
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| 4:20 pm - 5:00 pm | Ballroom 2 | | Test Bench Solution and Verification IP for Designing Artificial Intelligence SoCs [More Info]
Satyapriya Acharya, Synopsys
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| 5:00 pm - 5:30 pm | Ballroom 4 | | Best Paper Awards & Grand Lucky Draw [More Info] |
