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Advanced Layout Methods | Advanced Nodes | ||
Analog / Mixed-Signal | Analog Mixed-Signal / Debugging | ||
Arm IP | Automotive | ||
Automotive IP | Automotive ISO26262 Implementation | ||
Automotive ISO26262 Verification | Automotive Verification | ||
ECO and IP | EM-aware Parasitic Signoff | ||
Full Custom & Analog / Mixed Signal | General Sessions | ||
IP | Machine Learning | ||
Networking Opportunities | Physical Implementation | ||
Physical Verification | RTL Implementation | ||
Test | Verification Continuum | ||
Virtual Prototyping |
June 11, 2018 | ||||
12:00 - 13:00 | Foyer | Lunch [More Info] | ||
12:00 - 18:15 | Atrium | Registration [More Info] | ||
13:00 - 13:15 | Munich 1 | Welcome to SNUG Europe [More Info] Peter Rothenaicher, Synopsys | ||
13:15 - 14:15 | Munich 1 | Keynote: The Pace of Innovation [More Info] Marco Casale-Rossi, Member of the Office of the CTO, Synopsys | ||
14:45 - 15:30 | Frankfurt | Examining the Latest VCS AMS and Verdi AMS Features for Enhanced Usability and Debug During Mixed Signal Simulation and Verification [More Info] Peter Thompson, Synopsys | ||
14:45 - 15:30 | Bangkok 1 & 2 | Gigabit and Beyond, Next Gen Ethernet in Automotive [More Info] Andreas Kolof, Infineon Technologies AG | ||
14:45 - 15:30 | Munich 1 | Runtime-Tuning for Design Compiler [More Info] Ludovic Pinon, Synopsys | ||
15:30 - 16:15 | Frankfurt | Custom WaveView Updates and a Tutorial on Design Debugging Using DesignView [More Info] Michael Yang, Synopsys Manu Velayudhan Pillai, Synopsys | ||
15:30 - 16:15 | Munich 1 | DC R&D Update [More Info] Klaus Eckl, Synopsys GmbH | ||
15:30 - 16:15 | Bangkok 1 & 2 | NVM (Non-Volatile Memory) for Sensor Chips and Automotive Markets [More Info] Steven Oostdijk, Synopsys | ||
16:45 - 17:30 | Munich 1 | Achieving Out-of-the-Box Results with IC Compiler II [More Info] Frank De Meersman, Synopsys | ||
16:45 - 17:30 | Frankfurt | Custom Compiler Template-Based Design for Layout Automation [More Info] | ||
16:45 - 18:15 | Bangkok 1 & 2 | Developing and Testing Parallel Automotive Software on Multi-Core Virtual Prototypes using Synopsys Virtualizer [More Info] | ||
17:30 - 18:15 | Munich 1 | Achieving Best QoR and Fastest TAT with Synopsys Fusion Technology [More Info] | ||
17:30 - 18:15 | Frankfurt | IC Validator - Physical Signoff Challenges for all edges [More Info] | ||
18:45 - 22:00 | Off Site | Social Evening Event [More Info] | ||
June 12, 2018 | ||||
08:00 - 09:00 | Foyer | Breakfast [More Info] | ||
08:00 - 16:30 | Atrium | Registration [More Info] | ||
09:00 - 10:15 | Munich 1 | Welcome and Keynote - Fusion Innovations: Are You Ready? [More Info] Deirdre Hanford, co-General Manager Design Group, Corporate Staff, Synopsys | ||
10:45 - 11:15 | Munich 2 | Accessing Indirectly Addressed Register of a Design in the UVM Verification Environment [More Info] Joachim Geishauser, NXP | ||
10:45 - 11:15 | Munich 1 | Faster Timing Closure and Power Saving for VPU (Vision Processing Unit) SoC Intended for Deep Learning and AI Acceleration [More Info] | ||
10:45 - 11:15 | Frankfurt | Fixing Hold Violations by Adding Load in Metal ECO [More Info] Soenke Grimpen, Infineon | ||
10:45 - 11:15 | Bangkok 1 & 2 | Is the Default TetraMAX Transition Fault List Adequate? [More Info] Richard Illman, Dialog Semiconductor | ||
10:45 - 11:15 | Tokyo & Istanbul | Performance Analysis of AURIX™ 2G VP Using Synopsys Virtualizer™ [More Info] Aditya Raghunath, Infineon Technologies | ||
10:45 - 11:15 | New York | Unlocking the Power of SV in a Mixed Signal Simulation with Verilog-A [More Info] Peter Grove, Dialog Semiconductor | ||
11:15 - 11:45 | Tokyo & Istanbul | An Automated Behavioral Model Generation and Schematic Comparison Tool for Analog Circuits in SoC Validation [More Info] | ||
11:15 - 11:45 | New York | Custom MOSRA Model with Gate Voltage Effect for Aging Simulation [More Info] Kerwin Khu, TDK-Micronas GmbH Thomas Gneiting, AdMOS GmbH | ||
11:15 - 11:45 | Frankfurt | Signoff Power Analysis Driven PrimeTime ECO for Best PPA - Accelerated by Machine Learning [More Info] Gernot Gall, Synopsys GmbH | ||
11:15 - 11:45 | Munich 1 | Smart Compactor Digital Flow [More Info] Cyrille Conneradt, STMicroelectronics | ||
11:15 - 11:45 | Bangkok 1 & 2 | Using TetraMAX II ATPG on a 28nm ASIC SoC, a User Experience [More Info] Michael Kogan, EASii IC | ||
11:15 - 11:45 | Munich 2 | VC Formal: the Leap to Formal Verification [More Info] David Vincenzoni, STMicroelectronics | ||
11:45 - 12:15 | Munich 1 | 22FDx Low Voltage Design Deploying Dynamic Body Bias and Liberty Variation Format [More Info] Chenbo Liu, GLOBALFOUNDRIES | ||
11:45 - 12:15 | New York | A Simulation-Based Failure Rate Analysis for Automotive Applications Using CustomSimTM [More Info] Radu Iacob, Synopsys | ||
11:45 - 12:15 | Munich 2 | Case Study of Using Zebu Emulation [More Info] Niko Taipaleenmaki, Nokia | ||
11:45 - 12:15 | Tokyo & Istanbul | Enabling Fault Injection in an Automotive VP using Simulation Probes [More Info] Aditya Raghunath, Infineon Technologies | ||
11:45 - 12:15 | Bangkok 1 & 2 | Implementing Continuous LogicBist with Multiple Seeds to Comply with ISO26262 [More Info] Tim Paredaens, ICsense Valentin Simon, ICsense | ||
11:45 - 12:15 | Frankfurt | PCIe Gen4 Interface IP Subsystem Implementation Pushing the complexity boundaries in Design Closure in a case study based on a complete SNPS IP & EDA Ecosystem Solution [More Info] Ramin Navai, IDT | ||
12:15 - 14:00 | Atrium | Networking Lunch [More Info] | ||
14:00 - 14:30 | Bangkok 1 & 2 | A Case Study of Test Point Insertion for Improving Testability of Automotive Designs [More Info] Dr. Daniel Tille, Infineon Technologies AG | ||
14:00 - 14:30 | New York | Customsim XA and CCK Combined for Massive Productivity Boost [More Info] Lior Dagan, Dialog Semiconductor | ||
14:00 - 14:30 | Frankfurt | DTCO Flow for Device Exploration [More Info] Dmitry Yakimets, imec | ||
14:00 - 14:30 | Munich 2 | Reckoning Zebu Runtime Performance on DPI Function Calls [More Info] Marquette Anderson, Arm | ||
14:00 - 15:00 | Munich 1 | Best Practices for High-Performance, Energy Efficient Implementations of the Latest Arm Processors in 7-nanometer FinFET (7FF) Process Technology Using Synopsys Design Platform [More Info] Alan Gibbons, Synopsys Phil Morris, Arm | ||
14:00 - 15:00 | Tokyo & Istanbul | IC Validator Productivity & Performance in Physical Verification [More Info] David DeMarcos, Synopsys Christen Decoin, Synopsys | ||
14:30 - 15:00 | New York | Creating Common Centroid Layout with Custom Compiler [More Info] Gernot Koch, TDK-Micronas GmbH | ||
14:30 - 15:00 | Munich 2 | Multi-Modal CDC Structural Checks Flow [More Info] Maël Rabé, STMicroelectronics | ||
14:30 - 15:00 | Frankfurt | Sensitivity Study of the Parasitics of Advanced FinFETs [More Info] Pieter Schuddinck, imec | ||
14:30 - 15:00 | Bangkok 1 & 2 | Successful Chain Diagnosis in Complex SoC [More Info] Nelly Feldman, STMicroelectronics | ||
15:30 - 16:30 | Tokyo & Istanbul | AI Creating New Opportunities for Chip Designers [More Info] Dr. Yankin Tanurhan, Synopsys | ||
15:30 - 16:30 | Bangkok 1 & 2 | Bringing Digital Intelligence to the Synopsys Design Platform [More Info] Dr. Thomas Andersen, Synopsys | ||
15:30 - 16:30 | New York | Delivering Robust AMS Designs [More Info] Anand Thiruvengadam, Synopsys | ||
15:30 - 16:30 | Munich 2 | Functional Safety for Todays Complex SoCs [More Info] Jean-Marc Forey, Synopsys | ||
15:30 - 16:30 | Munich 1 | ISO 26262: Whats Required for Safety-Critical Semiconductor Designs? [More Info] Mary Ann White, Synopsys | ||
15:30 - 16:30 | Frankfurt | Nvidia's Electromagnetic-aware Sign-off Flow with Helic Exalto and Synopsys StarRC [More Info] Konstantis Daloukas, HELIC | ||
16:30 - 17:30 | Foyer | SNUG Pub and Awards [More Info] |
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