| 12:00 - 13:00 | Foyer | | Lunch [More Info] |
| 12:00 - 18:15 | Atrium | | Registration [More Info] |
| 13:00 - 13:15 | Munich 1 | | Welcome to SNUG Europe [More Info]
Peter Rothenaicher, Synopsys
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| 13:15 - 14:15 | Munich 1 | | Keynote: The Pace of Innovation [More Info]
Marco Casale-Rossi, Member of the Office of the CTO, Synopsys
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| 14:45 - 15:30 | Frankfurt | | Examining the Latest VCS AMS and Verdi AMS Features for Enhanced Usability and Debug During Mixed Signal Simulation and Verification [More Info]
Peter Thompson, Synopsys
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| 14:45 - 15:30 | Bangkok 1 & 2 | | Gigabit and Beyond, Next Gen Ethernet in Automotive [More Info]
Andreas Kolof, Infineon Technologies AG
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| 14:45 - 15:30 | Munich 1 | | Runtime-Tuning for Design Compiler [More Info]
Ludovic Pinon, Synopsys
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| 15:30 - 16:15 | Frankfurt | | Custom WaveView Updates and a Tutorial on Design Debugging Using DesignView [More Info]
Michael Yang, Synopsys
Manu Velayudhan Pillai, Synopsys
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| 15:30 - 16:15 | Munich 1 | | DC R&D Update [More Info]
Klaus Eckl, Synopsys GmbH
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| 15:30 - 16:15 | Bangkok 1 & 2 | | NVM (Non-Volatile Memory) for Sensor Chips and Automotive Markets [More Info]
Steven Oostdijk, Synopsys
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| 16:45 - 17:30 | Munich 1 | | Achieving Out-of-the-Box Results with IC Compiler II [More Info]
Frank De Meersman, Synopsys
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| 16:45 - 17:30 | Frankfurt | | Custom Compiler Template-Based Design for Layout Automation [More Info] |
| 16:45 - 18:15 | Bangkok 1 & 2 | | Developing and Testing Parallel Automotive Software on Multi-Core Virtual Prototypes using Synopsys Virtualizer [More Info] |
| 17:30 - 18:15 | Munich 1 | | Achieving Best QoR and Fastest TAT with Synopsys Fusion Technology [More Info] |
| 17:30 - 18:15 | Frankfurt | | IC Validator - Physical Signoff Challenges for all edges [More Info] |
| 18:45 - 22:00 | Off Site | | Social Evening Event [More Info] |
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| 08:00 - 09:00 | Foyer | | Breakfast [More Info] |
| 08:00 - 16:30 | Atrium | | Registration [More Info] |
| 09:00 - 10:15 | Munich 1 | | Welcome and Keynote - Fusion Innovations: Are You Ready? [More Info]
Deirdre Hanford, co-General Manager Design Group, Corporate Staff, Synopsys
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| 10:45 - 11:15 | Munich 2 | | Accessing Indirectly Addressed Register of a Design in the UVM Verification Environment [More Info]
Joachim Geishauser, NXP
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| 10:45 - 11:15 | Munich 1 | | Faster Timing Closure and Power Saving for VPU (Vision Processing Unit) SoC Intended for Deep Learning and AI Acceleration [More Info] |
| 10:45 - 11:15 | Frankfurt | | Fixing Hold Violations by Adding Load in Metal ECO [More Info]
Soenke Grimpen, Infineon
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| 10:45 - 11:15 | Bangkok 1 & 2 | | Is the Default TetraMAX Transition Fault List Adequate? [More Info]
Richard Illman, Dialog Semiconductor
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| 10:45 - 11:15 | Tokyo & Istanbul | | Performance Analysis of AURIX™ 2G VP Using Synopsys Virtualizer™ [More Info]
Aditya Raghunath, Infineon Technologies
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| 10:45 - 11:15 | New York | | Unlocking the Power of SV in a Mixed Signal Simulation with Verilog-A [More Info]
Peter Grove, Dialog Semiconductor
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| 11:15 - 11:45 | Tokyo & Istanbul | | An Automated Behavioral Model Generation and Schematic Comparison Tool for Analog Circuits in SoC Validation [More Info] |
| 11:15 - 11:45 | New York | | Custom MOSRA Model with Gate Voltage Effect for Aging Simulation [More Info]
Kerwin Khu, TDK-Micronas GmbH
Thomas Gneiting, AdMOS GmbH
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| 11:15 - 11:45 | Frankfurt | | Signoff Power Analysis Driven PrimeTime ECO for Best PPA - Accelerated by Machine Learning [More Info]
Gernot Gall, Synopsys GmbH
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| 11:15 - 11:45 | Munich 1 | | Smart Compactor Digital Flow [More Info]
Cyrille Conneradt, STMicroelectronics
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| 11:15 - 11:45 | Bangkok 1 & 2 | | Using TetraMAX II ATPG on a 28nm ASIC SoC, a User Experience [More Info]
Michael Kogan, EASii IC
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| 11:15 - 11:45 | Munich 2 | | VC Formal: the Leap to Formal Verification [More Info]
David Vincenzoni, STMicroelectronics
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| 11:45 - 12:15 | Munich 1 | | 22FDx Low Voltage Design Deploying Dynamic Body Bias and Liberty Variation Format [More Info]
Chenbo Liu, GLOBALFOUNDRIES
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| 11:45 - 12:15 | New York | | A Simulation-Based Failure Rate Analysis for Automotive Applications Using CustomSimTM [More Info]
Radu Iacob, Synopsys
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| 11:45 - 12:15 | Munich 2 | | Case Study of Using Zebu Emulation [More Info]
Niko Taipaleenmaki, Nokia
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| 11:45 - 12:15 | Tokyo & Istanbul | | Enabling Fault Injection in an Automotive VP using Simulation Probes [More Info]
Aditya Raghunath, Infineon Technologies
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| 11:45 - 12:15 | Bangkok 1 & 2 | | Implementing Continuous LogicBist with Multiple Seeds to Comply with ISO26262 [More Info]
Tim Paredaens, ICsense
Valentin Simon, ICsense
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| 11:45 - 12:15 | Frankfurt | | PCIe Gen4 Interface IP Subsystem Implementation Pushing the complexity boundaries in Design Closure in a case study based on a complete SNPS IP & EDA Ecosystem Solution [More Info]
Ramin Navai, IDT
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| 12:15 - 14:00 | Atrium | | Networking Lunch [More Info] |
| 14:00 - 14:30 | Bangkok 1 & 2 | | A Case Study of Test Point Insertion for Improving Testability of Automotive Designs [More Info]
Dr. Daniel Tille, Infineon Technologies AG
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| 14:00 - 14:30 | New York | | Customsim XA and CCK Combined for Massive Productivity Boost [More Info]
Lior Dagan, Dialog Semiconductor
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| 14:00 - 14:30 | Frankfurt | | DTCO Flow for Device Exploration [More Info]
Dmitry Yakimets, imec
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| 14:00 - 14:30 | Munich 2 | | Reckoning Zebu Runtime Performance on DPI Function Calls [More Info]
Marquette Anderson, Arm
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| 14:00 - 15:00 | Munich 1 | | Best Practices for High-Performance, Energy Efficient Implementations of the Latest Arm Processors in 7-nanometer FinFET (7FF) Process Technology Using Synopsys Design Platform [More Info]
Alan Gibbons, Synopsys
Phil Morris, Arm
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| 14:00 - 15:00 | Tokyo & Istanbul | | IC Validator Productivity & Performance in Physical Verification [More Info]
David DeMarcos, Synopsys
Christen Decoin, Synopsys
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| 14:30 - 15:00 | New York | | Creating Common Centroid Layout with Custom Compiler [More Info]
Gernot Koch, TDK-Micronas GmbH
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| 14:30 - 15:00 | Munich 2 | | Multi-Modal CDC Structural Checks Flow [More Info]
Maël Rabé, STMicroelectronics
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| 14:30 - 15:00 | Frankfurt | | Sensitivity Study of the Parasitics of Advanced FinFETs [More Info]
Pieter Schuddinck, imec
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| 14:30 - 15:00 | Bangkok 1 & 2 | | Successful Chain Diagnosis in Complex SoC [More Info]
Nelly Feldman, STMicroelectronics
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| 15:30 - 16:30 | Tokyo & Istanbul | | AI Creating New Opportunities for Chip Designers [More Info]
Dr. Yankin Tanurhan, Synopsys
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| 15:30 - 16:30 | Bangkok 1 & 2 | | Bringing Digital Intelligence to the Synopsys Design Platform [More Info]
Dr. Thomas Andersen, Synopsys
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| 15:30 - 16:30 | New York | | Delivering Robust AMS Designs [More Info]
Anand Thiruvengadam, Synopsys
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| 15:30 - 16:30 | Munich 2 | | Functional Safety for Todays Complex SoCs [More Info]
Jean-Marc Forey, Synopsys
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| 15:30 - 16:30 | Munich 1 | | ISO 26262: Whats Required for Safety-Critical Semiconductor Designs? [More Info]
Mary Ann White, Synopsys
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| 15:30 - 16:30 | Frankfurt | | Nvidia's Electromagnetic-aware Sign-off Flow with Helic Exalto and Synopsys StarRC [More Info]
Konstantis Daloukas, HELIC
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| 16:30 - 17:30 | Foyer | | SNUG Pub and Awards [More Info] |
