| 08:00 - 09:00 | Kerry Hotel Pudong, Shanghai | | Registration |
| 09:00 - 09:10 | Grand Shanghai Ballroom | | Opening Speech [More Info]
Magic Ge, Vice President and China Country Manager, Synopsys
|
| 09:10 - 09:50 | Grand Shanghai Ballroom | | Synopsys Keynote Speech [More Info]
Speaker: Dr. Chi-Foon Chan, President and co-Chief Executive Officer, Synopsys
|
| 09:50 - 10:00 | Grand Shanghai Ballroom | | Award Speech [More Info]
Qingyuan Zheng, SNUG China TC Chairperson
|
| 10:00 - 10:40 | Grand Shanghai Ballroom | | Partner Keynote Speech [More Info]
Xin Wang, 安波福电子与安全事业部亚太区工程总监
|
| 11:00 - 12:00 | Pudong Ballroom 1-3 | | Accelerating Robust Custom Design [More Info]
Dr. Paul Lo, Senior Vice President, Design Group , Synopsys
|
| 11:00 - 12:00 | Pudong Ballroom 5-7 | | Design and Verification Considerations for 5G SoC [More Info]
Peter Zhang, Mgr II, R&D, Synopsys
|
| 11:00 - 12:00 | Grand Shanghai Ballroom 1 | | Enabling Device Intelligence from the Data-Center to the Edge [More Info]
Stelios Diamantidis, Senior Product Marketing Manager, Synopsys
|
| 11:00 - 12:00 | Grand Shanghai Ballroom 2 | | Techniques to Accelerate Data Fusion in your SoC: High-Performance Sensor, Voice and Audio Processing [More Info] |
| 11:00 - 12:00 | Grand Shanghai Ballroom 3 | | Test Interaction with Functional Safety [More Info]
Adam Cron, Principal Applications Engineer, Synopsys
|
| 11:00 - 12:00 | Pudong Ballroom 4 | | Transform your RTL-to-GDSII Flow with Fusion Technology [More Info]
Mary Ann White, Director of Product Marketing, Galaxy Design Platform, Synopsys
|
| 12:00 - 13:00 | Grand Shanghai Ballroom | | Networking Lunch |
| 13:00 - 13:40 | Pudong Ballroom 1-3 | | 7-nm Design Tips for Performance, Power & Area Optimization [More Info]
Rahul Thukral, Synopsys
Kenneth Brock, Synopsys
|
| 13:00 - 13:40 | Grand Shanghai Ballroom 2 | | Accelerating Software Development in SoC with Zebu and Coverity [More Info]
Hainian Sun, Dahua
|
| 13:00 - 13:40 | Grand Shanghai Ballroom 3 | | ADAS SW development and integration on a Virtual Prototype at NXP and 1st Tier [More Info]
Sylvain Bayon de Noyer, NXP
Mingfei Bao, Synopsys
|
| 13:00 - 13:40 | Pudong Ballroom 4 | | Best Practices For High-performance, Energy Efficient Implementations of Arm® Next Generation Processors In 7-nanometer FinFET Compact (7FF) Process Technology Using Synopsys® Design Platform [More Info]
Felix Chen, Applications Engineer, Synopsys
|
| 13:00 - 13:40 | Grand Shanghai Ballroom 1 | | Bringing Digital Intelligence to the Design Platform [More Info]
Joe Walston, Principal Applications Engineer, Synopsys
|
| 13:00 - 13:40 | Pudong Ballroom 5-7 | | Software-Driven Power Analysis [More Info] |
| 13:40 - 14:20 | Pudong Ballroom 4 | | Emerging Node Design with IC Compiler II [More Info]
William Cheng, Senior Applications Engineer, Synopsys
|
| 13:40 - 14:20 | Grand Shanghai Ballroom 1 | | How to Help AI Chip FPGA Prototyping with HAPS [More Info] |
| 13:40 - 14:20 | Pudong Ballroom 1-3 | | HSPICE, FSIM, Custom Compiler, Custom WaveView Updates and How to Accelerate SPICE for Analog Simulation [More Info]
Gim Tan, Senior Applications Engineer, Synopsys
|
| 13:40 - 14:20 | Pudong Ballroom 5-7 | | Next Generation Memory Interfaces [More Info]
Brett Murdock, Senior Product Marketing Manager, Synopsys
|
| 13:40 - 14:20 | Grand Shanghai Ballroom 2 | | Next Generation Signoff Power and Reliability Analysis – Introduction and Tutorial [More Info]
James Chuang, Product Marketing Manager, Synopsys
|
| 13:40 - 14:20 | Grand Shanghai Ballroom 3 | | What’s Required for Safety-Critical Semiconductor Designs? [More Info]
Mary Ann White, Director of Product Marketing, Galaxy Design Platform, Synopsys
|
| 14:20 - 15:00 | Pudong Ballroom 4 | | 56G and 32G SerDes Enables Cloud Computing Applications with 100G/200G Ethernet and PCIe 5.0 [More Info]
Manmeet Walia, Senior Marketing Manager, Synopsys
|
| 14:20 - 15:00 | Grand Shanghai Ballroom 3 | | Accelerating Automotive ADAS SoC Development with ASIL Certified IP [More Info]
Ron DiGiuseppe, Senior Product Marketing Manager, Synopsys
|
| 14:20 - 15:00 | Pudong Ballroom 1-3 | | Body-Bias as Golden Fingers to Achieve High Performance on GLOBALFOUNDRIES 22FDX [More Info]
Bin Qi, GLOBALFOUNDRIES
|
| 14:20 - 15:00 | Pudong Ballroom 5-7 | | Hector Use Model on computing algorithm verification [More Info] |
| 14:20 - 15:00 | Grand Shanghai Ballroom 1 | | PrimeTime ECO Tutorial – 5X Faster Power Recovery with Machine Learning [More Info]
James Chuang, Product Marketing Manager, Synopsys
|
| 14:20 - 15:00 | Grand Shanghai Ballroom 2 | | Reduce MBIST Area Using Shared Wrapper [More Info]
Tuanhui Xu, Hisilicon
|
| 15:20 - 16:00 | Grand Shanghai Ballroom 3 | | Automotive - Functional Safety Verification [More Info] |
| 15:20 - 16:00 | Grand Shanghai Ballroom 1 | | DDR4 or HBM2 – How to Choose [More Info]
Brett Murdock, Senior Product Marketing Manager, Synopsys
|
| 15:20 - 16:00 | Pudong Ballroom 1-3 | | Physically-Aware Simulation and Electrical Analysis During with Fusion Technology [More Info]
Hung-Shih Wang, Technical Marketing Manager, Synopsys
Ray Jier Liu, Senior Applications Engineer, Synopsys
|
| 15:20 - 16:00 | Grand Shanghai Ballroom 2 | | RTL Power Optimization with SpyGlass Power Explorer [More Info] |
| 15:20 - 16:00 | Pudong Ballroom 5-7 | | Using the AMBA VIP to Integrate a C/C++ Processor Model in the RTL Simulation, and Debug with Verdi [More Info]
Xuhong, NXP
|
| 15:20 - 16:00 | Pudong Ballroom 4 | | What Advanced Node Support Means to Synthesis, What’s Changing and What it Promises to Deliver [More Info]
Carlos Abraham, Principal Applications Engineer, Synopsys
|
| 16:00 - 16:45 | Pudong Ballroom 4 | | Benefit from HyperScale Flow at Timing-closure Stage [More Info]
Marshal, Alchip
|
| 16:00 - 16:45 | Pudong Ballroom 4 | | Block Level Clock Tree Improvement [More Info]
Wayne Bai, AMD
|
| 16:00 - 16:45 | Grand Shanghai Ballroom 2 | | FastSpice – What’s New & The Application of Monte-Carlo in Mixed-Signal Simulation [More Info]
Eugene Lee, Senior Applications Engineer, Synopsys
|
| 16:00 - 16:45 | Pudong Ballroom 1-3 | | Industry Proven Solution to Achieve Fast Yield Ramp for New Products [More Info]
Chan Chen, Senior Applications Engineer, Synopsys
|
| 16:00 - 16:45 | Pudong Ballroom 5-7 | | Introduction to Reset Domain Crossings (RDC) [More Info] |
| 16:00 - 16:45 | Grand Shanghai Ballroom 3 | | Memory Test & Repair and Hierarchical Test of Interface IP for Automotive FinFET based SoC’s [More Info]
Faisal Goriawalla, Senior Product Marketing Manager, Synopsys
|
| 16:00 - 16:45 | Grand Shanghai Ballroom 1 | | VC Formal Apps Expansion: X-Prop and Register Verification [More Info]
Xiaolin Chen, Senior Applications Engineer, Synopsys
|
| 16:45 - 17:15 | Grand Shanghai Ballroom | | Lucky Draw [More Info] |
