| 9:00 am - 9:10 am | Meeting Room A | | Opening [More Info] |
| 9:10 am - 9:50 am | Meeting Room A | | Keynote - Evolution of Trust in a Changing Ecosystem [More Info]
Dr. Chi-Foon Chan, President and co-Chief Executive Officer, Synopsys
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| 9:50 am - 10:30 am | Meeting Room A | | Keynote - Taiwan AI Strategy Toward the Semiconductor Industry [More Info]
Dr. Yu-Chin Hsu, Deputy Minister, Ministry of Science and Technology
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| 10:30 am - 10:50 am | Meeting Room A | | Welcome and Technical Program Overview [More Info] |
| 11:20 am - 11:50 am | Meeting Room E | | Best Practices for Virtual Prototyping of Artificial Intelligence Accelerators and SoCs [More Info] |
| 11:20 am - 11:50 am | Meeting Room C | | ISO-26262 Compliant Automotive HW Design Verification [More Info] |
| 11:20 am - 11:50 am | Meeting Room D | | Technology Fusion of Synopsys Custom Design Platform [More Info] |
| 11:20 am - 11:50 am | Meeting Room A and B | | Transform your RTL-to-GDSII Flow with Fusion Technology [More Info] |
| 11:50 am - 12:20 pm | Meeting Room C | | Achieve Higher Test-Coverage with Functional Patterns, by Using Z01X Fault Simulator [More Info] |
| 11:50 am - 12:20 pm | Meeting Room D | | Silicon Smart Characterization Experience Sharing - Mixed Flow [More Info] |
| 11:50 am - 12:20 pm | Meeting Room E | | SOC Configuration Adjustment on HAPS with Protocompiler and Capim System [More Info] |
| 11:50 am - 12:20 pm | Meeting Room A and B | | TSMC-Synopsys Collaboration on N7+ Digital Design Enablement [More Info] |
| 12:20 pm - 2:00 pm | Feast | | Lunch [More Info] |
| 2:00 pm - 2:30 pm | Meeting Room E | | Best Practices for Low Power Implementations of Arm Cortex-A55 CPU Optimized with PrimeTime [More Info] |
| 2:00 pm - 2:30 pm | Meeting Room A | | Clock Trunk, Mesh, or H-tree, Which One Suits You Best? [More Info] |
| 2:00 pm - 2:30 pm | Meeting Room C | | Glitch Scaler — A New Approach to Model Glitch Power in Logic Simulation [More Info] |
| 2:00 pm - 2:30 pm | Meeting Room D | | TSMC-Synopsys Collaboration on N7+ Custom Design Enablement [More Info] |
| 2:00 pm - 3:00 pm | Meeting Room B | | Design Compiler QoR & Productivity Improvements & Advance Node Support [More Info] |
| 2:30 pm - 3:00 pm | Meeting Room C | | Enabling Power Estimation for SOC with DesignWare Building Block [More Info] |
| 2:30 pm - 3:00 pm | Meeting Room D | | Highspeed SERDES Verification with SNPS VCS+XA Solution [More Info] |
| 2:30 pm - 3:00 pm | Meeting Room E | | Huge Design Timing Analysis with PT HyperScale STA [More Info] |
| 2:30 pm - 3:00 pm | Meeting Room A | | Use ECO Fusion for Timing Closure and Galaxy Custom Routing for DDR Wire Matching Routing to Achieve Timing Closure Faster in 6M Large Flatten Design [More Info] |
| 3:00 pm - 3:30 pm | Meeting Room A | | Accelerate Time-to-Market with RedHawk™ Analysis Fusion and Maximize Design Robustness [More Info] |
| 3:00 pm - 3:30 pm | Meeting Room D | | FineSim Spice S-parameter simulation in Signal Integrity Analysis [More Info] |
| 3:00 pm - 3:30 pm | Meeting Room C | | High-Quality Early Power Estimation by Siloti Technology and DCE/DCG Floorplan Exploration [More Info] |
| 3:00 pm - 3:30 pm | Meeting Room E | | IR-Aware Timing Analysis for N16 High Speed Computing Design [More Info] |
| 3:00 pm - 3:30 pm | Meeting Room B | | Sharing IO Codec: Achieving the Highest Chip-level Test Coverage with Limited Scan Accessibility [More Info] |
| 4:00 pm - 4:30 pm | Meeting Room B | | Case Experience Sharing to Improve ATPG QoR with TetraMAXII [More Info] |
| 4:00 pm - 4:30 pm | Meeting Room A | | Cortex-A55 POPTM IP on 16FFC: Is Performance Still Vital? [More Info] |
| 4:00 pm - 4:30 pm | Meeting Room C | | DB or not DB? That is the Question - for Power Aware Simulation [More Info] |
| 4:00 pm - 4:30 pm | Meeting Room D | | New Custom Design Flow with Synopsys Custom Compiler [More Info] |
| 4:00 pm - 4:30 pm | Meeting Room E | | PrimeTime Reporting Runtime & Productivity Improvements [More Info] |
| 4:30 pm - 5:00 pm | Meeting Room C | | eDP RX v1.4 Verification by Using Synopsys DP Test Suite [More Info] |
| 4:30 pm - 5:00 pm | Meeting Room A | | High Efficiency and Reliability ICC2 HDP Flow on 12M SOC Design [More Info] |
| 4:30 pm - 5:00 pm | Meeting Room E | | Signoff Power Analysis Driven PrimeTime ECO for Best PPA - Accelerated by Machine Learning [More Info] |
| 4:30 pm - 5:00 pm | Meeting Room B | | SpyGlass DFT ADV Early Testability Analysis [More Info] |
| 4:30 pm - 5:30 pm | Meeting Room D | | Custom Compiler Schematic and Layout Assistants [More Info] |
| 5:00 pm - 5:30 pm | Meeting Room A | | Achieve Timing QoR Goal for CA7 with Robust N12 ICC2 Flow [More Info] |
| 5:00 pm - 5:30 pm | Meeting Room E | | Extreme Physical Verification Productivity Gains [More Info] |
| 5:00 pm - 5:30 pm | Meeting Room B | | Managing the Cost of Test in an Environment of Increasing Design Complexity Using Rapid and Predictable Quality Tests [More Info] |
| 5:00 pm - 5:30 pm | Meeting Room C | | VC Formal Apps Expansion: X-Prop and Register Apps [More Info] |
| 5:30 pm - 5:50 pm | Meeting Room A | | SNUG Taiwan Technical Committee Best Paper Award [More Info] |
| 5:50 pm - 7:00 pm | Meeting Room A | | Lucky Draw [More Info] |
