| 08:45 - 09:00 | Ballroom | Welcome |
| 09:00 - 10:00 | Ballroom I & II | Keynote - “More than Moore” Technologies - Arjun Kumar Kantimahanti, Vice President of Technology Development, Silterra |
| 13:30 - 14:30 | Ballroom I & II | Vision Address - Where Challenges Become Opportunities - Don Chan, Senior Vice President, Engineering, Synopsys |
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| 10:30 - 11:00 | Ballroom I & II | Efficient Hierarchical Timing Convergence for Mega SoCs [More Info] |
| 11:00 - 11:45 | Ballroom I & II | The Next Generation of HyperScale – Speed, Resource Efficiency and Added Flexibility - Synopsys [More Info] |
| 11:45 - 12:15 | Ballroom I & II | Slack Allocation Based Power Recovery [More Info] |
| 14:30 - 15:15 | Ballroom I & II | Getting the Best from Design Compiler Graphical Tool - Synopsys [More Info] |
| 15:45 - 16:15 | Ballroom I & II | In Design DFM Rule Scoring and Fixing Method Using ICV - GLOBALFOUNDRIES [More Info] |
| 16:15 - 17:00 | Ballroom I & II | Synopsys Automotive Test - ISO 26262-Certified Solution - Synopsys [More Info] |
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| 10:30 - 11:00 | Ballroom III | Electro-Migration Aware Block Size Estimator [More Info] |
| 11:00 - 11:45 | Ballroom III | IC Compiler II 2016.12 Update - Synopsys [More Info] |
| 11:45 - 12:15 | Ballroom III | ERC Fixing Tool [More Info] |
| 14:30 - 15:15 | Ballroom III | IC Compiler II-DP: Pipeline Register Planning - Synopsys [More Info] |
| 15:45 - 16:15 | Ballroom III | Sequential Repeater Planning Script [More Info] |
| 16:15 - 17:00 | Ballroom III | SiliconSmart - Characterize Low Voltage Swing Differential Transmitters with Verilog-A and Library Variation Format(LVF) for Advance Node Designs - Savarti, Synopsys [More Info] |
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| 08:00 - 08:45 | Grand Ballroom Foyer | Registration |
| 10:00 - 10:30 | Grand Ballroom Foyer | Tea Break |
| 12:15 - 13:30 | Matahari II & III | Networking Lunch |
| 15:15 - 15:45 | Grand Ballroom Foyer | Tea Break |
| 17:00 - 17:30 | Ballroom I & II | Best Paper Awards & Lucky Draw |
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| 10:30 - 11:00 | Matahari I | Choosing Formal Verification over Dynamic Simulation [More Info] |
| 10:30 - 11:00 | Ballroom I & II | Efficient Hierarchical Timing Convergence for Mega SoCs [More Info] |
| 10:30 - 11:00 | Ballroom III | Electro-Migration Aware Block Size Estimator [More Info] |
| 11:45 - 12:15 | Ballroom III | ERC Fixing Tool [More Info] |
| 11:45 - 12:15 | Matahari I | Hierarchical Clock Domain Crossing (CDC) Verification for Complex SoC Design [More Info] |
| 11:45 - 12:15 | Ballroom I & II | Slack Allocation Based Power Recovery [More Info] |
| 15:45 - 16:15 | Ballroom I & II | In Design DFM Rule Scoring and Fixing Method Using ICV - GLOBALFOUNDRIES [More Info] |
| 15:45 - 16:15 | Ballroom III | Sequential Repeater Planning Script [More Info] |
| 15:45 - 16:15 | Matahari I | Unified Constraint Practices for Clock Domain Crossing (CDC) and Static Timing Analysis (STA) [More Info] |
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| 10:30 - 11:00 | Matahari I | Choosing Formal Verification over Dynamic Simulation [More Info] |
| 11:00 - 11:45 | Matahari I | VCS Performance Innovations – Fine-Grained Parallelism and More! - Synopsys [More Info] |
| 11:45 - 12:15 | Matahari I | Hierarchical Clock Domain Crossing (CDC) Verification for Complex SoC Design [More Info] |
| 14:30 - 15:15 | Matahari I | Increase Your Verification Productivity with VC Formal - Synopsys [More Info] |
| 15:45 - 16:15 | Matahari I | Unified Constraint Practices for Clock Domain Crossing (CDC) and Static Timing Analysis (STA) [More Info] |
| 16:15 - 17:00 | Matahari I | Synopsys Verification IP Solution: Overcome Protocol Verification Challenges and Reduce the Verification Closure Time - Synopsys [More Info] |
