| 08:45 - 09:00 | Ballroom | Welcome |
| 13:30 - 14:30 | Ballroom 1 | Vision Address - Where Challenges Become Opportunities - Don Chan, Senior Vice President, Engineering, Synopsys |
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| 09:00 - 09:30 | Ballroom 1 | Standard Cell Library Evaluation with Multiple-Lithography-Compliant Verification and Improved Synopsys Pin Access Checking Utility - GLOBALFOUNDRIES [More Info] |
| 09:30 - 10:00 | Ballroom 1 | Effective Glitch Fixing Methodology for High Density Routing Channels - MediaTek [More Info] |
| 10:30 - 11:00 | Ballroom 1 | Accelerating High Performance SoCs to Market with Synopsys Galaxy Design Platform - Renesas [More Info] |
| 11:00 - 11:45 | Ballroom 1 | IC Compiler II 2016.12 Update - Synopsys [More Info] |
| 11:45 - 12:15 | Ballroom 1 | Predictive Clock Skew Redistribution Methodology for Improved Timing QoR [More Info] |
| 14:30 - 15:15 | Ballroom 1 | Getting the Best from DCG & Addressing PPA and TO Schedule Challenges with Design Compiler Graphical - Synopsys and Renesas [More Info] |
| 15:45 - 16:15 | Ballroom 1 | Incremental Floorplan ECO Flows for SoC Design [More Info] |
| 16:15 - 17:00 | Ballroom 1 | IC Compiler II-DP: Pipeline Register Planning - Synopsys [More Info] |
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| 09:00 - 09:30 | Ballroom 2 | Structural Verilog Based Full-Chip Simulation Using CustomSim-XA - Infineon [More Info] |
| 09:30 - 10:00 | Ballroom 2 | A Novel Mixed Signal Layout Approach For GHz High Speed IO Implementation - MediaTek [More Info] |
| 10:30 - 11:00 | Ballroom 2 | In Design DFM Rule Scoring and Fixing Method Using ICV - GLOBALFOUNDRIES [More Info] |
| 11:00 - 11:45 | Ballroom 2 | Using Custom Compiler’s Visually-Assisted Automation for Analog Layout - Synopsys [More Info] |
| 11:45 - 12:15 | Ballroom 2 | Renesas Shares the Improvement of Turn Around Time (TAT) by Using IC Compiler II - Custom Compiler Link to Perform High Precise Analog Signal Routing - Renesas [More Info] |
| 14:30 - 15:15 | Ballroom 2 | The Next Generation of HyperScale – Speed, Resource Efficiency and Added Flexibility - Synopsys [More Info] |
| 15:45 - 16:15 | Ballroom 2 | Automated Parametric Optimization of Custom IC Designs Using Python Script Wrappers - Lattice [More Info] |
| 16:15 - 17:00 | Ballroom 2 | Synopsys Automotive Test - ISO 26262-Certified Solution - Synopsys [More Info] |
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| 08:00 - 08:45 | Grand Ballroom Foyer | Registration |
| 10:00 - 10:30 | Grand Ballroom Foyer | Tea Break |
| 12:15 - 13:30 | Grand Ballroom Foyer | Networking Lunch |
| 15:15 - 15:45 | Grand Ballroom Foyer | Tea Break |
| 17:00 - 17:30 | Ballroom 1 | Best Paper Awards & Lucky Draw |
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| 09:00 - 09:30 | Napier & Read Room | Hybrid UVM Testbench for Interchangeable CPU and BFM Transactions - Realtek [More Info] |
| 09:00 - 09:30 | Ballroom 1 | Standard Cell Library Evaluation with Multiple-Lithography-Compliant Verification and Improved Synopsys Pin Access Checking Utility - GLOBALFOUNDRIES [More Info] |
| 09:00 - 09:30 | Ballroom 2 | Structural Verilog Based Full-Chip Simulation Using CustomSim-XA - Infineon [More Info] |
| 09:30 - 10:00 | Ballroom 2 | A Novel Mixed Signal Layout Approach For GHz High Speed IO Implementation - MediaTek [More Info] |
| 09:30 - 10:00 | Ballroom 1 | Effective Glitch Fixing Methodology for High Density Routing Channels - MediaTek [More Info] |
| 09:30 - 10:00 | Napier & Read Room | Integration Experience of Intel USB3.1 PHY with Synopsys USB3.1 Controller [More Info] |
| 10:30 - 11:00 | Ballroom 1 | Accelerating High Performance SoCs to Market with Synopsys Galaxy Design Platform - Renesas [More Info] |
| 10:30 - 11:00 | Ballroom 2 | In Design DFM Rule Scoring and Fixing Method Using ICV - GLOBALFOUNDRIES [More Info] |
| 10:30 - 11:00 | Napier & Read Room | Introduction to SpyGlass Reset Domain Crossings (RDC) - Synopsys [More Info] |
| 11:45 - 12:15 | Ballroom 1 | Predictive Clock Skew Redistribution Methodology for Improved Timing QoR [More Info] |
| 11:45 - 12:15 | Ballroom 2 | Renesas Shares the Improvement of Turn Around Time (TAT) by Using IC Compiler II - Custom Compiler Link to Perform High Precise Analog Signal Routing - Renesas [More Info] |
| 15:45 - 16:15 | Napier & Read Room | A Robust, Randomized, Reusable, Portable, Measurable, Systematic and Efficient Scheme for DUT Configuration in UVM - Realtek [More Info] |
| 15:45 - 16:15 | Ballroom 2 | Automated Parametric Optimization of Custom IC Designs Using Python Script Wrappers - Lattice [More Info] |
| 15:45 - 16:15 | Ballroom 1 | Incremental Floorplan ECO Flows for SoC Design [More Info] |
| |
| 09:00 - 09:30 | Napier & Read Room | Hybrid UVM Testbench for Interchangeable CPU and BFM Transactions - Realtek [More Info] |
| 09:30 - 10:00 | Napier & Read Room | Integration Experience of Intel USB3.1 PHY with Synopsys USB3.1 Controller [More Info] |
| 10:30 - 11:00 | Napier & Read Room | Introduction to SpyGlass Reset Domain Crossings (RDC) - Synopsys [More Info] |
| 11:00 - 11:45 | Napier & Read Room | VCS Performance Innovations – Fine-Grained Parallelism and More! - Synopsys [More Info] |
| 11:45 - 12:15 | Napier & Read Room | Functional Safety Verification for Automotive Designs - Synopsys [More Info] |
| 14:30 - 15:15 | Napier & Read Room | Increase Your Verification Productivity with VC Formal - Synopsys [More Info] |
| 15:45 - 16:15 | Napier & Read Room | A Robust, Randomized, Reusable, Portable, Measurable, Systematic and Efficient Scheme for DUT Configuration in UVM - Realtek [More Info] |
| 16:15 - 17:00 | Napier & Read Room | Synopsys Verification IP Solution: Overcome Protocol Verification Challenges and Reduce the Verification Closure Time - Synopsys [More Info] |
