| Automotive | |||
| Thursday, June 29, 2017 | |||
| 10:45 - 11:45 | Strauss B | Customer Keynote & Panel: Technology Trends and Dynamics in the Automotive Market [More Info] Luca DeAmbroggi, Principal Analyst, IHS Markit Joachim Kunkel, Executive Vice President and General Manager, Solutions Group, Synopsys Jeff Hutton, Synopsys | |
| 11:45 - 12:15 | Strauss B | ZOIX Evaluation in a Microcontroller [More Info] Martino Quattrocchi, STMicroelectronics | |
| 13:30 - 14:00 | Strauss B | Performance Analysis with ARM Cycle Models in Platform Architect for Next Generation Automotive Devices [More Info] Manfred Thanner, NXP Semiconductors | |
| 14:00 - 14:30 | Strauss B | Performance Analysis of an ADAS System with Synopsys Platform Architect MCO [More Info] Danilo Piergentili, Robert Bosch GmbH | |
| 14:30 - 15:00 | Strauss B | Behavioral Modeling of a Power Switch Drive IO Chip in Saber Platform [More Info] Saad Jabir, Nur-Engineering GmbH/Infineon | |
| 15:30 - 16:15 | Strauss B | Meeting IP Requirements of ADAS Automotive SoCs [More Info] Andreas Vielhaber, Synopsys | |
| 16:15 - 17:00 | Strauss B | Synopsys Automotive Test - ISO 26262-Certified Solution [More Info] Frank Nolting, Synopsys | |
| Digital Functional Verification | |||
| Thursday, June 29, 2017 | |||
| 10:45 - 11:15 | Studer | Verification of Multi-Cycle Path Timing Exceptions in Simulation with Automatically Generated SystemVerilog Assertions [More Info] Akshaya Prashanthi Lakshmi Narayanan, Infineon Technologies AG | |
| 11:15 - 11:45 | Studer | Introduction to Reset Domain Crossings [More Info] James Gillespie, Synopsys | |
| 11:45 - 12:15 | Studer | Driving Synchronizer Implementation from RTL Analysis [More Info] Carsten Rau, Infineon Technologies AG | |
| 13:30 - 14:30 | Studer | Boosting Debug Productivity with Verdi – Practical Applications of Debug Innovations [More Info] Jörg Richter, Synopsys | |
| 14:30 - 15:00 | Studer | Comprehensive Power Verification for Ultra-Low-Power SoC Designs [More Info] | |
| 15:30 - 16:15 | Studer | VCS Performance Innovations - Fine-Grained Parallelism and More! [More Info] Werner Kerscher, Synopsys | |
| 16:15 - 17:00 | Studer | VC Formal - Formal Verification with Assertion IPs [More Info] Laureano Carrasco, Synopsys | |
| Digital Implementation | |||
| Thursday, June 29, 2017 | |||
| 10:45 - 11:30 | Strauss A | Debugging and Resolving Failing and Inconclusive Verifications in Formality [More Info] Dr. Manuela Anton, Synopsys | |
| 11:30 - 12:15 | Strauss A | HyperScale: Next Generation Hierarchical Timing Sign-off [More Info] Gernot Gall, Synopsys | |
| 13:30 - 14:00 | Strauss A | Evaluation of TetraMAX II for Small Digital Designs in Mixed Signal Applications [More Info] Richard Illman, Dialog Semiconductor | |
| 14:00 - 14:30 | Strauss A | Automatic Test Point Insertion for MPHY Products [More Info] | |
| 14:30 - 15:00 | Strauss A | Physically Aware ATPG Testpoint Insertion in DCG/ICC [More Info] Jochen Neidhardt, BOSCH Sensortec | |
| 15:30 - 16:15 | Strauss A | Pipeline Register Planning using IC Compiler II [More Info] David Kingston, Synopsys | |
| 16:15 - 17:00 | Strauss A | IC Compiler II Release Update [More Info] David Kingston, Synopsys | |
| Digital Verification (IP/Prototyping) & Advanced Node Implementation | |||
| Thursday, June 29, 2017 | |||
| 10:45 - 11:45 | Bialas | A New Concept of UMRBus-based Verification Environment FPGA Acceleration: a Cycle-accurate Approach [More Info] Ilya Dmitrienko, Baikal Electronics Igor Suetinov, Baikal Electronics Philipp Jacobsohn, Synopsys | |
| 11:45 - 12:15 | Bialas | Creating Highly Reliable FPGA Designs [More Info] Philipp Jacobsohn, Synopsys | |
| 13:30 - 14:00 | Bialas | Minimizing Power of a 16nm 1.5M Instance RFSoC Digital Design using Design Compiler [More Info] Ryan Kinnerk, Xilinx | |
| 14:00 - 14:30 | Bialas | Hierarchical Design Exploration to find Automatic Body Bias Configuration to Achieve Optimal PPA for Globalfoundries 22 FD-SOI Technology [More Info] Askan Manger, GLOBALFOUNDRIES | |
| 14:30 - 15:00 | Bialas | Early Stage Rail Analysis of Complex SoC Design Using PrimeRail In-Design Flow [More Info] Dmitry Radchenko, Synopsys | |
| 15:30 - 16:15 | Bialas | Galaxy RTL: Design Compiler Family 2016.12 Update [More Info] Frederic Genin, Synopsys | |
| 16:15 - 17:00 | Bialas | ICV In-Design Flow with IC Compiler II [More Info] Dmitry Radchenko, Synopsys | |
| Full Custom & Analog / Mixed Signal | |||
| Thursday, June 29, 2017 | |||
| 10:45 - 11:15 | Orff | Utilizing VCS AMS for High Performance Mixed Signal Verification [More Info] Peter Thompson, Synopsys | |
| 11:15 - 11:45 | Orff | Variation Block Monte-Carlo in CustomSim and VCS-AMS - Modelling and Application [More Info] Haiko Morgenstern, Infineon Technologies AG | |
| 11:45 - 12:15 | Orff | Toggle Coverage at the Digital/Analog Boundary for Mixed Signal Simulations with VCS AMS [More Info] Alessandro Valerio, STMicroelectronics | |
| 13:30 - 14:00 | Orff | Integration of High-voltage Driver Made Easy with Synopsys Custom Compiler and a Python-based Layout Automation Flow [More Info] Melanie Wilhelm, X-FAB Semiconductor Foundries AG | |
| 14:00 - 14:30 | Orff | Technology-Independent Programmable Schematics (Schematic PCells) [More Info] Gernot Koch, TDK-Micronas GmbH | |
| 14:30 - 15:00 | Orff | Custom Compiler Customization for ST Design Flows [More Info] Sébastien Mathieu, STMicroelectronics | |
| 15:30 - 17:00 | Orff | Using Custom Compiler’s Visually-Assisted Automation for Analog and Custom Digital Layout [More Info] Damian Roberts, Synopsys | |
| General Sessions | |||
| Thursday, June 29, 2017 | |||
| 08:00 - 09:00 | Strauss Foyer | Breakfast | |
| 08:00 - 18:30 | Strauss Foyer | Registration | |
| 09:00 - 10:15 | Strauss Ballroom | Keynote - From Silicon to Software, Smartness Is Everything [More Info] Joachim Kunkel, Executive Vice President and General Manager, Solutions Group, Synopsys | |
| 12:15 - 13:30 | Zum Gasteig (Hotel Restaurant) | Networking Lunch | |
| 17:00 - 18:30 | Strauss Foyer | Awards and Refreshments | |
| User Content Reviewed by the Technical Committee | |||
| Thursday, June 29, 2017 | |||
| 10:45 - 11:45 | Bialas | A New Concept of UMRBus-based Verification Environment FPGA Acceleration: a Cycle-accurate Approach [More Info] Ilya Dmitrienko, Baikal Electronics Igor Suetinov, Baikal Electronics Philipp Jacobsohn, Synopsys | |
| 10:45 - 11:15 | Studer | Verification of Multi-Cycle Path Timing Exceptions in Simulation with Automatically Generated SystemVerilog Assertions [More Info] Akshaya Prashanthi Lakshmi Narayanan, Infineon Technologies AG | |
| 11:15 - 11:45 | Orff | Variation Block Monte-Carlo in CustomSim and VCS-AMS - Modelling and Application [More Info] Haiko Morgenstern, Infineon Technologies AG | |
| 11:45 - 12:15 | Studer | Driving Synchronizer Implementation from RTL Analysis [More Info] Carsten Rau, Infineon Technologies AG | |
| 11:45 - 12:15 | Orff | Toggle Coverage at the Digital/Analog Boundary for Mixed Signal Simulations with VCS AMS [More Info] Alessandro Valerio, STMicroelectronics | |
| 11:45 - 12:15 | Strauss B | ZOIX Evaluation in a Microcontroller [More Info] Martino Quattrocchi, STMicroelectronics | |
| 13:30 - 14:00 | Strauss A | Evaluation of TetraMAX II for Small Digital Designs in Mixed Signal Applications [More Info] Richard Illman, Dialog Semiconductor | |
| 13:30 - 14:00 | Bialas | Minimizing Power of a 16nm 1.5M Instance RFSoC Digital Design using Design Compiler [More Info] Ryan Kinnerk, Xilinx | |
| 13:30 - 14:00 | Strauss B | Performance Analysis with ARM Cycle Models in Platform Architect for Next Generation Automotive Devices [More Info] Manfred Thanner, NXP Semiconductors | |
| 14:00 - 14:30 | Strauss A | Automatic Test Point Insertion for MPHY Products [More Info] | |
| 14:00 - 14:30 | Strauss B | Performance Analysis of an ADAS System with Synopsys Platform Architect MCO [More Info] Danilo Piergentili, Robert Bosch GmbH | |
| 14:00 - 14:30 | Orff | Technology-Independent Programmable Schematics (Schematic PCells) [More Info] Gernot Koch, TDK-Micronas GmbH | |
| 14:30 - 15:00 | Strauss B | Behavioral Modeling of a Power Switch Drive IO Chip in Saber Platform [More Info] Saad Jabir, Nur-Engineering GmbH/Infineon | |
| 14:30 - 15:00 | Studer | Comprehensive Power Verification for Ultra-Low-Power SoC Designs [More Info] | |
| 14:30 - 15:00 | Orff | Custom Compiler Customization for ST Design Flows [More Info] Sébastien Mathieu, STMicroelectronics | |
| 14:30 - 15:00 | Strauss A | Physically Aware ATPG Testpoint Insertion in DCG/ICC [More Info] Jochen Neidhardt, BOSCH Sensortec | |
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