| Frontend Implementation | |||
| Thursday, April 27, 2017 | |||
| 10:45 am - 11:30 am | Salon G | Power and Supply Voltage: Contradicting Conventional Wisdom [More Info] Speaker: Rishi Yadav, The MITRE Corporation Speaker: Nimit Nguansiri, Lead Integrated Electronics Engineer, The MITRE Corporation | |
| 11:30 am - 12:15 pm | Salon G | The Challenges with Level Shifter Insertion Failure and How Classification Can Help [More Info] | |
| 1:15 pm - 2:15 pm | Salon G | DC Update From R&D's Perspective [More Info] Speaker: Janet Olson, Synopsys | |
| 2:45 pm - 3:15 pm | Salon G | What's New for UPF 3.0 on the Galaxy Platform [More Info] Speaker: John Geremia, Synopsys | |
| 3:30 pm - 4:15 pm | Salon G | PrimeTime 2016.12 Highlights [More Info] Speaker: Joseph Thomas, Synopsys | |
| 4:15 pm - 5:00 pm | Salon G | Accelerating ECO Implementation Using Formality Ultra [More Info] Speaker: Steve Lamb, Synopsys | |
| General Sessions | |||
| Thursday, April 27, 2017 | |||
| 9:15 am - 10:30 am | Salon D/E | Keynote - Silicon to Software to Smart Everything [More Info] Speaker: Dr. Aart de Geus, Chairman & co-CEO, Synopsys | |
| Networking Opportunities | |||
| Thursday, April 27, 2017 | |||
| 8:00 am - 9:15 am | Hallway | Breakfast [More Info] | |
| 8:00 am - 5:00 pm | No location | Registration [More Info] | |
| 12:15 pm - 1:15 pm | Salon D/E | Networking Lunch | |
| 5:00 pm - 7:00 pm | Salon D/E | SNUG Pub and Awards Presentation [More Info] | |
| Physical Design | |||
| Thursday, April 27, 2017 | |||
| 10:45 am - 11:30 am | Salon A/B | Global Clock Construction Using ICC2 [More Info] Speaker: Tom Meneghini, SMTS, Advanced Micro Devices, Inc. | |
| 11:30 am - 12:15 pm | Salon A/B | Improving Productivity of DRC and Density on Hierarchically Abutted Designs [More Info] | |
| 1:15 pm - 1:45 pm | Salon A/B | Leveraging Lynx to Automate Template Based Power Network Synthesis (TPNS) for Power Plan Regression and Analysis [More Info] Speaker: Priyam Patel, Physical Design Engineer, Microchip Technology | |
| 1:45 pm - 2:15 pm | Salon A/B | Efficient Convergence and Integration of Hierarchical Analog HIPs [More Info] | |
| 2:15 pm - 2:45 pm | Salon A/B | Custom Design Solution for High Speed Routing Channel [More Info] | |
| 2:45 pm - 3:15 pm | Salon A/B | Pipeline Register Planning [More Info] Speaker: David Peart, Synopsys | |
| 3:30 pm - 4:15 pm | Salon A/B | IC Compiler II 2016.12 Update [More Info] Speaker: Dave Power, Synopsys | |
| 4:15 pm - 5:00 pm | Salon A/B | Best Practices for High-Performance, Energy Efficient Implementations of the Latest ARM® Processors in 16-nanometer FinFET Compact (16FFC) Process Technology Using Synopsys Galaxy™ Design Platform [More Info] Speaker: Joe Walston, Synopsys | |
| SpyGlass | |||
| Thursday, April 27, 2017 | |||
| 4:15 pm - 5:00 pm | Salon C | Understanding Clock-Gating to Optimize Power at RTL [More Info] Speaker: Ken Mason, Synopsys | |
| Systems, FPGA & Prototyping | |||
| Thursday, April 27, 2017 | |||
| 10:45 am - 11:30 am | Salon C | Enabling High Reliability and Functional Safety for FPGA Based Hardware Design [More Info] Speaker: Carl Cleaver, Synopsys | |
| 11:30 am - 12:15 pm | Salon C | Introduction to CDC and Reset Checks for FPGA and ASIC Designers [More Info] Speaker: Greg Milano, Synopsys | |
| 1:15 pm - 1:55 pm | Salon C | GPU Prototyping With HAPS [More Info] Speaker: Kris Dobecki, Synopsys | |
| 1:55 pm - 2:35 pm | Salon C | Advanced Debug Techniques for HAPS Prototyping [More Info] Speaker: Bob Efram, Synopsys | |
| 2:35 pm - 3:15 pm | Salon C | Optimizing Cache Coherent Subsystem Architecture for Heterogeneous Multicore SoCs [More Info] Speaker: Pat Sheridan, Synopsys Speaker: Kurt Shuler, Arteris Speaker: Bill Neifert, ARM | |
| Test | |||
| Thursday, April 27, 2017 | |||
| 3:30 pm - 4:15 pm | Salon F | Meet Your Test Quality and Cost Goals with Unprecedented Speed [More Info] Speaker: Mona Marmash, Synopsys | |
| 4:15 pm - 5:00 pm | Salon F | SpyGlass® DFT ADV: High Testability, SoC Connectivity, Functional Safety and Reliability [More Info] Speaker: Fadi Maamari, Synopsys | |
| User Content Reviewed by the Technical Committee | |||
| Thursday, April 27, 2017 | |||
| 10:45 am - 11:30 am | Salon A/B | Global Clock Construction Using ICC2 [More Info] Speaker: Tom Meneghini, SMTS, Advanced Micro Devices, Inc. | |
| 10:45 am - 11:30 am | Salon G | Power and Supply Voltage: Contradicting Conventional Wisdom [More Info] Speaker: Rishi Yadav, The MITRE Corporation Speaker: Nimit Nguansiri, Lead Integrated Electronics Engineer, The MITRE Corporation | |
| 11:30 am - 12:15 pm | Charles River | Expeditious Verification Debug [More Info] | |
| 11:30 am - 12:15 pm | Salon A/B | Improving Productivity of DRC and Density on Hierarchically Abutted Designs [More Info] | |
| 11:30 am - 12:15 pm | Salon G | The Challenges with Level Shifter Insertion Failure and How Classification Can Help [More Info] | |
| 1:15 pm - 1:55 pm | Charles River | Clock Gater Verification using Formal Property Checking [More Info] Speaker: Alfonso Urzua, Senior Staff Engineer, Advanced Micro Devices, Inc. | |
| 1:15 pm - 1:45 pm | Salon A/B | Leveraging Lynx to Automate Template Based Power Network Synthesis (TPNS) for Power Plan Regression and Analysis [More Info] Speaker: Priyam Patel, Physical Design Engineer, Microchip Technology | |
| 1:45 pm - 2:15 pm | Salon A/B | Efficient Convergence and Integration of Hierarchical Analog HIPs [More Info] | |
| 1:55 pm - 2:35 pm | Charles River | Formal Coverage for Verification Sign-Off [More Info] Speaker: Roger Sabbagh, VP of Applications Engineering, Oski Technology Speaker: Anders Nordstrom, Synopsys | |
| 2:15 pm - 2:45 pm | Salon A/B | Custom Design Solution for High Speed Routing Channel [More Info] | |
| 2:35 pm - 3:15 pm | Charles River | Modeling and Verification of a PCIe Store Ordering Widget [More Info] Speaker: Shahid Ikram, Cavium | |
| 3:30 pm - 4:00 pm | Charles River | UVM Test Bench for Analog and Mixed Signal Design of a Generic SerDes Interface [More Info] Speaker: John Sweeney, Senior Consulting Engineer, Cavium | |
| 4:00 pm - 4:30 pm | Charles River | Expanding On Traditional Cosim Methodologies with VCS AMS (CustomSim-VCS) [More Info] Speaker: John Brennan, Cavium | |
| 4:30 pm - 5:00 pm | Charles River | Managing Register Side Effects and Exceptions with UVM 1.2 RAL [More Info] Speaker: Steven K. Sherman, Verification Engineer, Advanced Micro Devices, Inc. | |
| Verification Continuum | |||
| Thursday, April 27, 2017 | |||
| 10:45 am - 11:30 am | Charles River | VCS Performance Innovations - Fine-Grained Parallelism and More! [More Info] Speaker: David Hsu, Synopsys | |
| 11:30 am - 12:15 pm | Charles River | Expeditious Verification Debug [More Info] | |
| 1:15 pm - 1:55 pm | Charles River | Clock Gater Verification using Formal Property Checking [More Info] Speaker: Alfonso Urzua, Senior Staff Engineer, Advanced Micro Devices, Inc. | |
| 1:55 pm - 2:35 pm | Charles River | Formal Coverage for Verification Sign-Off [More Info] Speaker: Roger Sabbagh, VP of Applications Engineering, Oski Technology Speaker: Anders Nordstrom, Synopsys | |
| 2:35 pm - 3:15 pm | Charles River | Modeling and Verification of a PCIe Store Ordering Widget [More Info] Speaker: Shahid Ikram, Cavium | |
| 3:30 pm - 4:00 pm | Charles River | UVM Test Bench for Analog and Mixed Signal Design of a Generic SerDes Interface [More Info] Speaker: John Sweeney, Senior Consulting Engineer, Cavium | |
| 4:00 pm - 4:30 pm | Charles River | Expanding On Traditional Cosim Methodologies with VCS AMS (CustomSim-VCS) [More Info] Speaker: John Brennan, Cavium | |
| 4:30 pm - 5:00 pm | Charles River | Managing Register Side Effects and Exceptions with UVM 1.2 RAL [More Info] Speaker: Steven K. Sherman, Verification Engineer, Advanced Micro Devices, Inc. | |
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