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Cloud | Custom Implementation and AMS | ||
Frontend Implementation | Frontend/Physical Implementation | ||
General Sessions | Networking Opportunities | ||
Physical Implementation | Test | ||
User Content Reviewed by the Technical Committee | Verification Continuum HW | ||
Verification Continuum SW |
Wednesday, September 11, 2019 | |||||
7:45 am - 6:30 pm | Foyer | Registration [More Info] | |||
9:00 am - 10:15 am | Governor's Ballroom | Keynote: High Impact Innovation [More Info] Sassine Ghazi, General Manager Design Group, Corporate Staff, Synopsys | |||
10:30 am - 11:10 am | 410 | Chip-Level IDDQ Current Simulation and Leaky Path Detection using CustomSim [More Info] Jianjun Liu, Design Automation Engineer, Medtronic | |||
10:30 am - 11:10 am | 408 | Functional Coverage on Emulation [More Info] | |||
10:30 am - 11:10 am | 406 | Verification of a Modern Branch Predictor [More Info] Ken Matthews, Performance Modeling, Samsung Ashutosh Moghe, Staff Engineer, Samsung | |||
10:30 am - 11:30 am | Salon D/E | Realizing Best-in-Class QoR and the Fastest Time-to-Market with the Synopsys Fusion Design Platform [More Info] James Harper, Synopsys | |||
11:10 am - 11:50 am | 406 | All Your Base Transactions Belong to Us [More Info] Jeff Vance, Design Verification Engineer, Verilab | |||
11:10 am - 11:50 am | 410 | Chip-Level Verification of an RF ASIC with CustomSim/VCS [More Info] Greg Tumbush, Verification Manager, EM Microelectronic | |||
11:10 am - 11:50 am | 408 | U-boot and Linux Bring-up of Automotive SoC on ZeBu [More Info] Lan Nguyen, Design Engineer, NXP Semiconductors Bharadwaj Ramanujam, Senior Principal Emulation Engineer, NXP Semiconductors Dhruvesh Shah, Emulation Lead, NXP Semiconductors | |||
11:30 am - 12:30 pm | Salon D/E | Solving Design Problems and Maximizing Productivity with the Fusion Compiler GUI [More Info] John Griner, Synopsys | |||
11:50 am - 12:30 pm | 410 | Analog Design Closure with Custom Compiler [More Info] Soni Kapoor, Senior Technical Marketing Manager, Synopsys | |||
11:50 am - 12:30 pm | 406 | What's New in VCS/Verdi [More Info] David Lee, Applications Engineer, Synopsys | |||
11:50 am - 12:30 pm | 408 | zSV Connect: Methodology to Connect ZeBu to VCS for UVM Monitor Reuse with zdpiReport Post-processing [More Info] Sameer Ghewari, ZeBu Applications Engineer, Synopsys | |||
12:30 pm - 1:45 pm | Governor's Ballroom | Networking Lunch [More Info] | |||
1:45 pm - 2:25 pm | Salon E | Detailed Bus Planning Using IC Compiler II Create Route Tool [More Info] Pamela Smoot, MTS ASIC/Layout Design Engineer, Advanced Micro Devices | |||
1:45 pm - 2:25 pm | Salon D | Graphic Core IP Power Optimization Using minPower Guided and SAIF Driven Synthesis [More Info] Chris Meng, PMTS, Advanced Micro Devices | |||
1:45 pm - 2:25 pm | 408 | HAPS - ZeBu Companion Flow for IP Design [More Info] | |||
1:45 pm - 2:25 pm | 410 | Test Case to Share RAM Sequential ATPG Improvement Efforts and Results with Synopsys TetraMAX II [More Info] Maheshkumar Devani, Senior Staff Engineer - DFT, MediaTek | |||
1:45 pm - 2:25 pm | 406 | “Shift Left” using Design Independent UPF Checking and Hierarchical Low Power Static Verification using Signoff Abstract Model (SAM) [More Info] Bharani Ellore, Member Technical Staff, Advanced Micro Devices | |||
2:25 pm - 3:05 pm | Salon D | Design Compiler® NXT – Latest Advances [More Info] Danny Bradley, Principal Applications Engineer, Synopsys Jason Perez, Sr. Circuit Designer, NXP Semiconductors | |||
2:25 pm - 3:05 pm | 410 | Effectiveness of Testpoints with SpyGlass DFT ADV on the Qualcomm Hexagon DSP [More Info] Preston McWithey, Sr. Staff Engineer, Qualcomm Shwetha Shivashankar Murthy, DFT Engineer, Qualcomm | |||
2:25 pm - 3:05 pm | 408 | Hybrid Emulation – The New Frontier Shifting Left High-level OS/SW Development [More Info] Jon McCallum, ZeBu Applications Engineer, Synopsys Mojin Kottarathil, Staff Applications Engineer, Synopsys | |||
2:25 pm - 3:05 pm | Salon E | Planning for Success; DP Solutions for Large and Complex Designs [More Info] Jim Schultz, Product Marketing Manager, Digital Design Implementation, Synopsys | |||
2:25 pm - 3:05 pm | 406 | Solving Simulation vs. Synthesis Mismatches with VC-Formal AEP and FXP [More Info] Alan Carlin, SoC Verification Engineer, NXP Semiconductors | |||
3:05 pm - 3:45 pm | 410 | DFT Shifts Left to Accelerate Time to Results [More Info] Giri Podichetty, Synopsys | |||
3:05 pm - 3:45 pm | Salon D | Formality Interactive and Automatic ECO Solutions [More Info] Steve Lamb, Synopsys | |||
3:05 pm - 3:45 pm | 406 | Machine Learning RCA Cutting Debug Time by 10X [More Info] Himanshu Bhatt, Senior Manager Applications Engineer, Synopsys Rahul Chirania, Staff Application Engineer, Synopsys | |||
3:05 pm - 3:45 pm | Salon E | Working Hard and Smart - Physical Verification Productivity Solutions using IC Validator [More Info] Jonathan White, Director - Physical Verification Application Engineering, Synopsys | |||
3:05 pm - 3:45 pm | 408 | ZeBu Emulation for Automotive SoC: Transactor Integration and Performance [More Info] Siddharth Satyapriya, Design Engineer, NXP Semiconductors Dhruvesh Shah, Emulation Lead, NXP Semiconductors | |||
4:00 pm - 4:30 pm | Salon D | Bottom-Up Timing Constraints Integration [More Info] Joseph Yang, Design Manager, Xilinx | |||
4:00 pm - 4:30 pm | Salon E | Clocking Challenges is Advanced ADAS SoCs [More Info] Rajeev Srivastava, Sr Principal Physical Design Engineer, NXP Semiconductors | |||
4:00 pm - 4:45 pm | 410 | Scaling Verification Workloads on the Cloud [More Info] Melvin Cardozo, Sr. MTS, Synopsys Jyotsna Repaka, Customer Engineer, Google Cloud | |||
4:00 pm - 4:45 pm | 406 | Want Functional Coverage Closure? Don’t Kneel to the Almighty Random Constraint Solver [More Info] Jeremy Ridgeway, Verification Architect, Broadcom | |||
4:00 pm - 5:30 pm | 408 | Boosting Regression Performance – Advanced Simulation Acceleration [More Info] Hillel Miller, Principle Engineer, Synopsys | |||
4:30 pm - 5:00 pm | Salon D | SMVA-based Efficient Approach to Analyze Impact of Supply Variations on Timing Closure in a Multi-voltage Design [More Info] Kishan Ganapathi, Senior Design Engineer, Xilinx | |||
4:30 pm - 5:30 pm | Salon E | Block Level CTS Debug With IC Compiler II [More Info] Pete Churchill, Synopsys | |||
4:45 pm - 5:30 pm | 406 | Automotive Functional Safety [More Info] Jiri Prevatil, Applications Engineer, Synopsys | |||
4:45 pm - 5:30 pm | 410 | Physical Verification on the Cloud - Solving Physical Signoff TAT Challenges [More Info] Jonathan White, Director - Physical Verification Application Engineering, Synopsys | |||
5:00 pm - 5:30 pm | Salon D | Latest Advances in PrimeTime-ADVPlus to Address Design Closure at 5nm and Below [More Info] Troy Epperly, Senior Staff Applications Engineer, Synopsys | |||
5:30 pm - 7:00 pm | Governor's Ballroom | SNUG Pub and Awards Ceremony [More Info] |
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