| Tuesday 11/20/2018 | Aerospace and Defense Verification Seminar - Israel The overall complexity and size of FPGA designs has grown significantly, driving the need for very high quality verification over the past several years. A device failure can result in loss of information, property or worse, life. Security checking, DO-254 design assurance, UVM methodologies, low-power checking, formal property checking, verification intent specification and traceability, total coverage models and fault injection capabilities are methods that have become a requirement in today’s FPGA Aerospace and Defense products. |  |
| Tuesday 11/27/2018 | Functional Safety Test Workshop for Automotive SoCs Developing SoCs for Safety Critical Applications Synopsys Functional Safety Test Solution Processor Safety Island for ARC Self Test and Repair and ECC for Memories STAR Hierarchical System for Analog and Mixed-Signal Interfaces LogicBIST for Logic Blocks Functional Safety Verification ARC Processors for Functional Safety | |
| Tuesday 12/04/2018 | TCAD Reception at IEDM 2018 After a day of conference sessions, attend the Synopsys TCAD Reception at IEDM 2018 in San Francisco, CA. | |
| Friday 12/07/2018 | Workshop: Ethernet PHY Design Methodology and Hands-On Custom Compiler Experience Map: https://goo.gl/maps/U4Acfcrht5K2 At this workshop, you will hear from the Synopsys DesignWare IP team about our high-speed 56G Ethernet PHY IP design project’s key findings, illustrating how designers can optimize their design methodology to overcome challenges, while meeting aggressive schedules. Attendees will go through a hands-on experience using Custom Compiler’s productive layout features, which helped the Synopsys IP team optimize their design methodology for successful design and delivery of 56G Ethernet PHY. In this workshop, you will: • Learn about the need for high-speed PHY technology for 400G and beyond Ethernet applications and what design considerations and methodology flows are required for such high-speed Ethernet SoCs • Use the Custom Compiler design environment to build a voltage regulator amplifier layout in 3X less time and minimize circuit/layout design iteration by extracting early parasitics, and checking and fixing electro migrations issues sooner Agenda 10:45 - 11:00 a.m. Welcome/Registration/Networking 11:00 - 12:00 p.m. Latest Innovations in 56G Ethernet PHY Presentation 12:00 - 1:00 p.m. Lunch and Custom Compiler Overview Presentation 1:00 - 2:30 p.m. Hands-On Experience with Custom Compiler: Amplifier Layout Design Visually-Assisted Automation for Analog Layout | |
| Wednesday 01/30/2019 | SaberES Designer Seminar 2019 Learn how our customers and partners are using Saber to address their design challenges. Learn from Synopsys engineers how a new harness architecture solution, advanced modeling and automation, and electrical system design and verification technologies will help quickly deliver innovative new designs to the vehicle market place that meet or exceed the emerging new standards. | |
