| Wednesday 09/12/2018 | Find and Fix Bugs Faster in FPGA and ASIC Designs - Irvine The overall complexity and size of ASIC and FPGA designs has grown significantly, driving the need for very high quality verification over the past several years. A device failure can result in loss of information, property or worse, life. Security checking, DO-254 design assurance, UVM methodologies, low-power checking, formal property checking, verification intent specification and traceability, total coverage models and fault injection capabilities are methods that have become a requirement in today’s FPGA and ASIC Aerospace and Defense products. |  |
| Wednesday 09/19/2018 | Find and Fix Bugs Faster in FPGA and ASIC Designs - San Diego The overall complexity and size of ASIC and FPGA designs has grown significantly, driving the need for very high quality verification over the past several years. A device failure can result in loss of information, property or worse, life. Security checking, DO-254 design assurance, UVM methodologies, low-power checking, formal property checking, verification intent specification and traceability, total coverage models and fault injection capabilities are methods that have become a requirement in today’s FPGA and ASIC Aerospace and Defense products. | |
| Tuesday 09/25/2018 | UK Technology Symposium 2018 Technical Symposium focusing on critical aspects of doing state of the art designs at established and emerging nodes. | |
| Wednesday 09/26/2018 | ASIP Universtity Day and Tutorial 2018 - Europe | |
| Thursday 09/27/2018 | France Technology Symposium 2018 | |
| Tuesday 10/09/2018 | FPGA and ASIC Verification Seminar for FPGA Projects (VA) The overall complexity and size of ASIC and FPGA designs has grown significantly, driving the need for very high quality verification over the past several years. A device failure can result in loss of information, property or worse, life. Security checking, DO-254 design assurance, UVM methodologies, low-power checking, formal property checking, verification intent specification and traceability, total coverage models and fault injection capabilities are methods that have become a requirement in today’s FPGA and ASIC products. | |
| Wednesday 10/10/2018 | 2018 年 ARC 处理器上海峰会 Synopsys 诚挚邀请您参加 2018 年 ARC® 处理器上海峰会。这是一天的免费会议，由 Synopsys 专家、ARC 用户以及 ARC 的生态系统合作伙伴主讲，内容覆盖人工智能、汽车安全、物联网、嵌入式视觉等等精彩内容。欢迎参加会议,了解嵌入式处理器 IP，软件，编程工具与应用领域的最新科技与趋势。 | |
| Tuesday 11/20/2018 | FPGA and ASIC Verification Seminar - Israel The overall complexity and size of ASIC and FPGA designs has grown significantly, driving the need for very high quality verification over the past several years. A device failure can result in loss of information, property or worse, life. Security checking, DO-254 design assurance, UVM methodologies, low-power checking, formal property checking, verification intent specification and traceability, total coverage models and fault injection capabilities are methods that have become a requirement in today’s FPGA and ASIC Aerospace and Defense products. | |
| Wednesday 01/30/2019 | SaberES Designer Seminar 2019 Learn how our customers and partners are using Saber to address their design challenges. Learn from Synopsys engineers how a new harness architecture solution, advanced modeling and automation, and electrical system design and verification technologies will help quickly deliver innovative new designs to the vehicle market place that meet or exceed the emerging new standards. | |
