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Design Implementation I | Design Implementation II | ||
Design Implementation III | General Sessions | ||
Networking Opportunities | Verification Continuum I | ||
Verification Continuum II |
Friday, September 27, 2019 | ||||
8:00 am - 9:25 am | Grand Ballroom Foyer | Registration / Networking Breakfast [More Info] | ||
9:25 am - 9:40 am | Grand Ballroom | Welcome [More Info] Jonathan Cheah, Synopsys | ||
9:40 am - 10:20 am | Grand Ballroom | Keynote: High Impact Innovation [More Info] Sassine Ghazi, Sassine Ghazi - General Manager Design Group, Corporate Staff, Synopsys | ||
10:25 am - 11:05 am | Grand Ballroom | Keynote: How UX in the Era of AI Transforms the Electronics Industry [More Info] Mario Traeber, Head of R&D SoC, Intel | ||
11:10 am - 11:35 am | Sky Ballroom 3 | AXI4 Assertion IP Usage in Formal Property Verification [More Info] Shuang Xiu Chuang, MediaTek | ||
11:10 am - 11:35 am | Sky Ballroom 2 | eCG : Foresee and Optimize Critical Clock Gate Timing in preCTS Using Machine Learning [More Info] Virender Singh, MediaTek | ||
11:10 am - 11:35 am | Sky Ballroom 1 | How to Handle Missing PST UPF ECO at SoC Top Level? A Multi-Million Gate-Count SoC Experience Sharing [More Info] Saurabh Sharma, Infineon | ||
11:10 am - 11:35 am | The Boardroom | Intel Gateway SoC Hybrid Prototyping with Industry Standard AMBA-based Transactors [More Info] | ||
11:40 am - 12:00 pm | The Boardroom | Dataflow Based Performance Analysis of Multi-SoC Networking Systems [More Info] | ||
11:40 am - 12:20 pm | Sky Ballroom 1 | Design Compiler® NXT and Power Compiler - Tutorial Covering Latest Release Updates [More Info] Phuong Nguyen, Synopsys | ||
11:40 am - 12:20 pm | Sky Ballroom 3 | High Performance Formal Verification: A Perfect Use of Machine Learning Techniques / VC-Formal’s Case Study and Success in Collaboration with Synopsys [More Info] Jonathan Cheah, Synopsys Pham Van Khich, Renesas Vietnam | ||
11:40 am - 12:20 pm | Sky Ballroom 2 | IC Compiler II Update [More Info] Kim Hong Soon, Synopsys | ||
12:00 pm - 12:20 pm | The Boardroom | Multi-FPGA Design Partitioning Methodology for Intel Gateway SoC [More Info] | ||
12:20 pm - 1:35 pm | Grand Ballroom Foyer | Networking Lunch [More Info] | ||
1:35 pm - 2:00 pm | Sky Ballroom 1 | Congestion Prevention Synthesis Flow to Address MUX Connectivity Challenge with Design Compiler [More Info] Khai Sean Yeoh, Xilinx | ||
1:35 pm - 2:00 pm | The Boardroom | Data Skew Optimization For Mixed Signal High-Speed Layout Design [More Info] Yen Min Tsai, MediaTek | ||
1:35 pm - 2:00 pm | Sky Ballroom 2 | Standard Cell Routability and DFM Checking with Synopsys Tools [More Info] Zhao Chuan Lee, GLOBALFOUNDRIES | ||
1:35 pm - 2:00 pm | Sky Ballroom 3 | VCS FGP Technology in Simulation Acceleration [More Info] Hiep Hguyen, Renesas Vietnam | ||
2:05 pm - 2:45 pm | Sky Ballroom 2 | Block Level CTS Debug with IC Compiler II [More Info] Hong Wai Tan, Synopsys | ||
2:05 pm - 2:45 pm | The Boardroom | Efficient Monte Carlo Solution Including High Sigma Designs and Update on Accelerating Simulation of High Accuracy Analog Designs [More Info] Xi Jiang, Synopsys | ||
2:05 pm - 2:45 pm | Sky Ballroom 1 | Machine Learning Accelerated ECO and Latest Advances with PrimeTime-ADVPlus [More Info] Arvinraj Applasamy, Synopsys | ||
2:05 pm - 2:45 pm | Sky Ballroom 3 | Using Simulation Acceleration to Speed Block and Platform Level IP Verification [More Info] Sivaprasad Acharaya, Synopsys | ||
2:50 pm - 3:15 pm | Sky Ballroom 1 | Accelerating Faster Time to Result Through Next Generation of RTL-to-GDSII Implementation Tool [More Info] | ||
2:50 pm - 3:15 pm | Sky Ballroom 2 | Automated Slack Based Register Cell Clock Latency Reduction for High Frequency Domain Timing Closure [More Info] | ||
2:50 pm - 3:15 pm | Sky Ballroom 3 | Case Study: Effective Approach to Detect Race Conditions in SoC – VCS Interactive Debugging to the Rescue [More Info] Abdus Samad Khan, Realtek Pooja Yogesh Jawandhiya, Realtek | ||
2:50 pm - 3:15 pm | The Boardroom | Full Flow Physical Verification Productivity using IC Validator [More Info] Lihui Yang, Synopsys | ||
3:20 pm - 4:00 pm | Sky Ballroom 1 | Best Practices using Synopsys Fusion Technology to Achieve High-Performance, Energy Efficient Implementations of the Latest Arm® Processors in 7-Nanometer FinFET (7FF) Process Technology [More Info] Sandeep Jain, Synopsys | ||
3:20 pm - 4:00 pm | Sky Ballroom 2 | Drive Faster Signoff Closure and Eliminate ECO Iterations with ECO Fusion [More Info] Ayush Katial, Synopsys | ||
3:20 pm - 4:00 pm | Sky Ballroom 3 | Early UPF Checking and Hierarchical Low Power Static Verification [More Info] Lay Fang Hoe, Synopsys | ||
3:20 pm - 4:00 pm | The Boardroom | TestMax Platform – DFT Shifts Left to Accelerate Time to Results! [More Info] Siva Kumar Etikala, Synopsys | ||
4:00 pm - 4:30 pm | Grand Ballroom Foyer | Tea Break [More Info] | ||
4:30 pm - 5:10 pm | Grand Ballroom | Common Technology Session - Energy Efficient ASIC Methodology [More Info] Godwin Maben, Synopsys | ||
5:10 pm - 5:30 pm | Grand Ballroom | Best Paper Awards & Lucky Draw! [More Info] |
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