| 7:45 am - 6:30 pm | Sheraton | | Registration [More Info] |
| 9:15 am - 10:30 am | Grand Ballroom | | Keynote: Change and Trust [More Info]
Speaker: Dr. Chi-Foon Chan, President and co-Chief Executive Officer, Synopsys
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| 10:45 am - 11:15 am | Ashland | | Automating High Performance Designs with Limited Area Resources [More Info] |
| 10:45 am - 11:30 am | Wayland | | Achieving 10X Performance on DFT Simulations [More Info]
Speaker: Jerry Fremaint, DFT Engineer, Broadcom
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| 10:45 am - 11:30 am | Concord | | Circuit Extraction with Parameterized Spice Netlists [More Info]
Speaker: Srilata Raman, Parasitic Extraction Engineer, GLOBALFOUNDRIES
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| 10:45 am - 11:30 am | Carlisle | | Supercharging SoC Prototyping [More Info] |
| 10:45 am - 11:30 am | Middlesex | | What’s New in PrimeTime 2019.03 [More Info]
Speaker: Bob Grozier, Synopsys
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| 11:15 am - 11:45 am | Ashland | | High Cell Density and Metal Utilization Design for a Mixed-signal, Multiply Instantiated Module [More Info] |
| 11:30 am - 12:15 pm | Wayland | | Elevate Verdi Waveform Debugging with Python [More Info]
Speaker: Mike Schaffstein, Principal Hardware Engineer, Dover Microsystems
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| 11:30 am - 12:15 pm | Concord | | Full Flow Physical Verification Productivity using IC Validator [More Info]
Speaker: Bob Strohl, Synopsys
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| 11:30 am - 12:15 pm | Middlesex | | Introduction to PrimePower and SoC Early Power Estimation Challenges and Accuracy [More Info]
Speaker: John Geremia, Synopsys
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| 11:30 am - 12:15 pm | Carlisle | | Squeezing the Highest Performance Out of Your Emulator [More Info] |
| 11:45 am - 12:15 pm | Ashland | | Tetromining Your Top Metal Layers [More Info] |
| 12:15 pm - 1:30 pm | Grand Ballroom | | Networking Lunch [More Info] |
| 1:30 pm - 2:10 pm | Ashland | | Clock Routing with IC Compiler II [More Info]
Speaker: Tom Meneghini, SMTS, Advanced Micro Devices
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| 1:30 pm - 2:10 pm | Wayland | | Switch It Up - Introducing NVIDIA's NVSwitch Bring Up and Testing Environment [More Info]
Speaker: Melanie Bianchi, Verification Engineer, NVIDIA
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| 1:30 pm - 2:10 pm | Concord | | Why is Design Constraints (SDC) Validation Critical at RTL? [More Info]
Speaker: Greg Milano, Synopsys
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| 1:30 pm - 2:20 pm | Carlisle | | Verification for Functional Safety [More Info]
Speaker: Brian Davenport, Synopsys
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| 1:30 pm - 3:00 pm | Middlesex | | Design Compiler® NXT and Power Compiler - Latest Release Updates [More Info]
Speaker: Bob Wiegand, Synopsys
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| 2:10 pm - 2:50 pm | Ashland | | Cooking Up the Perfect CTS Recipe [More Info] |
| 2:10 pm - 2:50 pm | Wayland | | Error Handling Verification - Challenges, Solutions, and Automation [More Info]
Speaker: Vinoth Selvan, ASIC Design Verification Engineer, NVIDIA
Speaker: Siraj Syed, Senior Design Verification Engineer, NVIDIA
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| 2:10 pm - 2:50 pm | Concord | | Using SpyGlass Lint to Achieve High Fmax on an FPGA [More Info]
Speaker: Jeffrey Benagh, Teradyne
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| 2:20 pm - 2:40 pm | Carlisle | | Using HAPS Prototyping Solutions to Perform HW/SW Validation for Complex AI SoCs [More Info]
Speaker: Rick Furtner, Synopsys
Speaker: Kris Dobecki, Synopsys
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| 2:40 pm - 3:30 pm | Carlisle | | Billion-Cycle Power Estimation using Fast Emulation [More Info]
Speaker: Alex Wakefield, Synopsys
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| 2:50 pm - 3:30 pm | Concord | | Avoid Silicon Respins with Netlist CDC Verification [More Info]
Speaker: Greg Milano, Synopsys
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| 2:50 pm - 3:30 pm | Ashland | | Block Level CTS Debug With IC Compiler II [More Info]
Speaker: Pete Churchill, Synopsys
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| 2:50 pm - 3:30 pm | Wayland | | Reducing Build Problems and Verification Issues in SoC Integration [More Info]
Speaker: Sergey Bogdanov, Advanced Micro Devices
Speaker: Mark Firstenberg, Advanced Micro Devices
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| 3:00 pm - 3:30 pm | Middlesex | | Formality 2018.06 and 2019.03 Technology Update [More Info]
Speaker: Steve Lamb, Synopsys
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| 3:45 pm - 4:30 pm | Wayland | | Hardware Unit Testing using Formal Verification [More Info]
Speaker: Anamaya Sullerey, Juniper Networks
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| 3:45 pm - 4:30 pm | Concord | | It's a Wrap!: Improve Productivity Using Hierarchical ATPG [More Info]
Speaker: Irfan Baig, Lead DFT Architect, Acacia Communications
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| 3:45 pm - 4:30 pm | Ashland | | Realizing Best-in-Class QoR and the Fastest Time-to-Market with the Synopsys Fusion Design Platform [More Info]
Speaker: James Harper, Product Applications Engineer, Synopsys
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| 4:30 pm - 5:15 pm | Wayland | | Bigger and Better - Intel's Experiences with Next Generation Static Low Power and UPF Verification Solutions [More Info] |
| 4:30 pm - 5:15 pm | Concord | | DFT Shifts Left to Accelerate Time to Results [More Info]
Speaker: Adam Cron, Synopsys
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| 4:30 pm - 5:15 pm | Ashland | | Where Are We on the Road to Artificial Intelligence in Chip Design? [More Info]
Speaker: Joe Walston, Synopsys
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| 5:15 pm - 7:15 pm | Grand Ballroom | | SNUG Pub and Awards Ceremony [More Info] |
