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Custom Implementation and AMS | General Sessions | ||
IP and Signoff | Networking Opportunities | ||
Physical Implementation | RTL Implementation and Test | ||
Verification Continuum 1 | Verification Continuum 2 |
08/05/2019 | ||||
9:00 am - 9:10 am | Meeting Room A and B | Opening [More Info] | ||
9:10 am - 9:50 am | Meeting Room A and B | Synopsys Keynote : Design in 2019 - What is Required and What Sets Us Apart [More Info] Speaker: Deirdre Hanford, co-General Manager Design Group, Corporate Staff, Synopsys | ||
9:50 am - 10:30 am | Meeting Room A and B | Keynote: IC Technology - The Golden Age of Innovation [More Info] Speaker: H.-S. Philip Wong, Vice President, Corporate Research, TSMC | ||
10:30 am - 10:50 am | Meeting Room A and B | Welcome and Program Overview [More Info] Speaker: WL Hsu, Director, Nuvoton Technology Corp. | ||
10:50 am - 11:20 am | NA | BREAK [More Info] | ||
11:20 am - 12:00 pm | Meeting Room E | Accelerating Data Connectivity for AI Computing with High-Speed Interface IP [More Info] Speaker: Ron DiGiuseppe, Senior Strategic Marketing Manager, Synopsys | ||
11:20 am - 12:00 pm | Meeting Room D | Custom Compiler and Laker FPD Update [More Info] Speaker: Mingi Lai, Senior Product AE, Synopsys Speaker: Dragon Peng, FAE, Synopsys | ||
11:20 am - 12:00 pm | Meeting Room A and B | Synopsys Fusion Platform for Best QoR & Fast TTR [More Info] Speaker: Mike Montana, Principal Engineer, Synopsys | ||
11:20 am - 12:00 pm | Meeting Room C | Synopsys Verification Solution Overview [More Info] Speaker: David Hsu, Director of Product Marketing, Synopsys | ||
12:00 pm - 1:30 pm | Buffet Restaurant | LUNCH [More Info] | ||
1:30 pm - 1:50 pm | Meeting Room D | TSMC-Synopsys Collaboration on N5 Custom Design [More Info] Speaker: Hsin-Po Wang, Technical Manager, TSMC | ||
1:30 pm - 2:00 pm | Meeting Room C | Achieving Predictable Functional & Performance Verification Closure of Complex Interconnect Subsystems: Synopsys VC Automation Solutions & VC VIP [More Info] Speaker: Alvin Chen, Application Engineering Manager, Synopsys | ||
1:30 pm - 2:00 pm | Meeting Room F | Billion-Cycle Power Estimation using Fast Emulation & Design AI Chips using Platform Architecture Ultra [More Info] Speaker: Jessy Chen, Sr. Application Engineer, Synopsys Speaker: Jack Lyu, Sr. Application Engineer, Synopsys | ||
1:30 pm - 2:10 pm | Meeting Room A | Best practices using Synopsys Fusion Technology to achieve high-performance, energy efficient implementations of the latest Arm® processors in 7-nanometer FinFET (7FF) Process Technology [More Info] Speaker: Mike Montana, Principal Engineer, Synopsys Speaker: Ryan Yuan, Staff applications engineer, Arm | ||
1:30 pm - 2:15 pm | Meeting Room E | Machine Learning Accelerated ECO and Latest Advances with PrimeTime-ADVPlus [More Info] Speaker: Brad Lee, Applications Engineer, Synopsys | ||
1:30 pm - 2:30 pm | Meeting Room B | Design Compiler® NXT, Power Compiler, and Formality - Tutorial covering Latest Release Updates [More Info] Speaker: Peter Tseng, Application Consultant, Synopsys | ||
1:50 pm - 3:30 pm | Meeting Room D | Accelerating Robust Design and Verification for High Speed I/O and Mixed-signal Design [More Info] Speaker: Gim Tan, Applications Engineer, Sr Staff, Synopsys Speaker: Hung-Shih Wang, Technical Marketing Manager, Synopsys | ||
2:00 pm - 2:30 pm | Meeting Room F | Prototyping Platform of Emulation, ZeBu-Companion, which Targets on Software Development Congruency [More Info] Speaker: Daniel Wu, MediaTek | ||
2:00 pm - 2:30 pm | Meeting Room C | Test Grading Mechanism Applied to Entire System Test Package [More Info] Speaker: Ming Lung Tsai, Technical Manager, MediaTek | ||
2:10 pm - 2:40 pm | Meeting Room A | In-Design Voltage Drop Optimization and Auto Fixing Solution [More Info] Speaker: Shih-An Hsieh, MediaTek Speaker: Winnie Pao, Manager, MediaTek | ||
2:15 pm - 3:00 pm | Meeting Room E | PrimeTime Productivity Improvement: DMSA Best Practices & IMSA Roll-Up Reporting [More Info] Speaker: Andi Lee, Application Consultant, Synopsys | ||
2:30 pm - 3:00 pm | Meeting Room C | How about Siloti (Verdi’s) Power Analysis Acceleration (PAA) without RTL Code? [More Info] Speaker: Yu-Shuan Liao, MediaTek | ||
2:30 pm - 3:00 pm | Meeting Room F | SSD Product Verification with ZeBu [More Info] Speaker: Eddy Kao, Silicon Motion | ||
2:30 pm - 3:00 pm | Meeting Room B | Using DesignCompiler for Power and Area Optimization based on Multi-Vt Library [More Info] Speaker: Kenny Chen, Technical Manager, MediaTek | ||
2:40 pm - 3:00 pm | Meeting Room A | Htree-only (no-mesh) Regular MSCTS incorporate with CCD for Arm Cortex-A73 with multiple clocks using IC Compiler II to improve QoR based on RM script [More Info] Babbit Chang, Novatek | ||
3:00 pm - 3:30 pm | Meeting Room A | Drive Faster Signoff Closure and Eliminate ECO Iteration with ECO Fusion [More Info] Speaker: Queenie Wang, Synopsys | ||
3:00 pm - 3:30 pm | Meeting Room C | Early UPF checking and Hierarchical Low Power Static Verification [More Info] Speaker: Tiger Hsu, Staff Engineer, Synopsys | ||
3:00 pm - 3:30 pm | Meeting Room B | High Precision Design and Implementation Techniques with Cascading Floating point DW IPs [More Info] Speaker: Yenyu Chen, Senior Engineer, MediaTek | ||
3:00 pm - 3:30 pm | Meeting Room F | Powerful and Efficient Verification: Synopsys LPDDR VIP [More Info] Speaker: Sara Kuo, Application Engineer, Synopsys | ||
3:00 pm - 3:30 pm | Meeting Room E | PrimeTime 2019.03 Update [More Info] Speaker: Robert Lin, Applications Engineer, Synopsys | ||
3:30 pm - 4:00 pm | NA | BREAK [More Info] | ||
4:00 pm - 4:30 pm | Meeting Room D | Analog Fault Simulation: A Systematic Approach to Ensuring Functional Safety and Low Defect Rate in Automotive ICs [More Info] Speaker: Robert Chuang, AE Manager, Synopsys | ||
4:00 pm - 4:30 pm | Meeting Room B | DFT Shifts Left to Accelerate Time to Results! [More Info] Speaker: DM Lee, Senior R&D Engineer, Synopsys | ||
4:00 pm - 4:30 pm | Meeting Room C | Effective RTL Analysis and Exploration to Reduce Power [More Info] Speaker: Chung-Chih Pan, Sr. RD Manager, Himax | ||
4:00 pm - 4:30 pm | Meeting Room F | HAPS Auxiliary FPGA Board Solutions - For AI and 16+/32 Gbps Transceiver Prototyping Applications [More Info] Speaker: Peter Zhang, Sr. R&D Manager, Synopsys | ||
4:00 pm - 4:30 pm | Meeting Room A | Physical Verification TAT Reduction with Unified PV Platform [More Info] Speaker: Sheng-Te Lai, MediaTek | ||
4:00 pm - 4:45 pm | Meeting Room E | No Vectors? No Problem! Analyzing Power Earlier with PrimePower 2019 [More Info] Speaker: Dennis Lin, Applications Engineer, Synopsys | ||
4:30 pm - 5:00 pm | Meeting Room D | Accelerate circuit design in Memory field with using Custom Compiler Environments [More Info] Speaker: Chien-Lung Chen, Technical Manager, Winbond | ||
4:30 pm - 5:00 pm | Meeting Room C | High Performance Formal Verification : A Perfect use of Machine Learning Techniques [More Info] Speaker: Penny Yang, Senior Formal Specialist, Synopsys | ||
4:30 pm - 5:00 pm | Meeting Room A | How to Control ICG During ICC2 Placement and CTS Stages [More Info] Speaker: Ryan Chen, GUC | ||
4:30 pm - 5:00 pm | Meeting Room B | Leveraging Test Fusion for Optimal PPA [More Info] Speaker: Elddie Tsai, Senior Applications Engineer, Synopsys | ||
4:30 pm - 5:00 pm | Meeting Room F | Methodology to Prototype Millions ASIC Gates Design in Multi-HAPS-80 System [More Info] Speaker: Vext Chen, Senior Technical Manager, MediaTek | ||
4:45 pm - 5:30 pm | Meeting Room E | Advanced Analysis/Debugging with StarRC Parasitic Explorer [More Info] Speaker: TK Yang, Applications Engineer, Synopsys | ||
5:00 pm - 5:30 pm | Meeting Room C | Formal Datapath Verification: VC Formal DPV using HECTOR Technology [More Info] Speaker: Penny Yang, Senior Formal Specialist, Synopsys | ||
5:00 pm - 5:30 pm | Meeting Room A | IC Compiler II Update [More Info] Speaker: ZY Lin, Synopsys | ||
5:00 pm - 5:30 pm | Meeting Room B | Maximized Reused Core Wrapper Flow: A Whole Chip Test Solution Making the Road to 0 DPPM More Possible [More Info] Speaker: Polin Chen, Associated Project Manager, Realtek | ||
5:00 pm - 5:30 pm | Meeting Room F | Remote FPGA Prototyping Access Using Synopsys HAPS Farm Infrastructure [More Info] Speaker: Gary Hsu, Senior Engineer, Phison | ||
5:00 pm - 5:30 pm | Meeting Room D | SAE with Advanced Analysis Emphasis [More Info] Speaker: Yi-Da Wu, Technical Manager, M31 | ||
5:30 pm - 6:30 pm | Meeting Room C | SNUG Taiwan 2019 Best Paper Award and Lucky Draw [More Info] Speaker: WL Hsu, Director, Nuvoton Technology Corp. |
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