| 7:30 am - 5:00 pm | Jamavar | | Registration [More Info] |
| 9:00 am - 10:15 am | Grand Ballroom | | Keynote - At the Heart of Impact [More Info]
Dr. Aart de Geus, Chairman & co-CEO, Synopsys
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| 10:30 am - 11:00 am | Turret | | Next Generation Safety Focused Testing [More Info]
Pramod Notiyath, Synopsys
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| 10:30 am - 11:30 am | Royal Ballroom | | VC Formal Apps Expansion: Security, X-Prop and Registers Verification [More Info]
Sanjana Bhattacharya, Synopsys
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| 10:30 am - 11:45 am | Grand Ballroom | | Extending the Frontiers of Digital Design with Synopsys Fusion Technologies [More Info]
Neeraj Kaul, Synopsys
Sanjay Bali, Synopsys
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| 11:00 am - 11:30 am | Turret | | Reducing Design Turn Around Time & Test ECO's using SpyGlass RTL DFT Checks [More Info]
Sanjoy Nanda, Qualcomm
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| 11:30 am - 12:00 pm | Royal Ballroom | | Above and Beyond: Enable Shift-Left in Datapath Designs Using Design Exercise and RTL [More Info] |
| 11:30 am - 12:00 pm | Turret | | UPF AWARE Scan Construction [More Info] |
| 11:45 am - 12:15 pm | Grand Ballroom | | A Comprehensive Strategy to Resolve Methodology Issues for High-Performance ASIC's in 7nm [More Info]
Biswajit Maity, Broadcom
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| 11:45 am - 12:15 pm | Jamavar | | Tips and Tricks to Fix hold on 100% Utilized Regions of High Frequency Designs [More Info]
Gurjot Singh Bakhshi, NXP
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| 12:00 pm - 12:30 pm | Turret | | Accelerating LOES Timing Closure on a High Performance Multimillion SoC [More Info]
Mahesh Rawal, Broadcom
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| 12:00 pm - 12:45 pm | Royal Ballroom | | Using Machine Learning to Improve Overall Verification Engineering Productivity, Quality, and Cost - Synopsys Case Studies [More Info]
Arun Venkatachar, Synopsys
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| 12:15 pm - 12:45 pm | Jamavar | | Effective Constraints Analysis for High Silicon Yield and Improved Implementation QoR [More Info]
Satyanarayana Medarametla, AMD
Raghu Pattipati, AMD
Payal Agarwal, AMD
Tejesh Ejanthkar, AMD
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| 12:15 pm - 12:45 pm | Grand Ballroom | | Routing Convergence for High Performance Designs at Advanced Technology Nodes [More Info]
Shanmugapriya Murugesan, AMD
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| 12:30 pm - 1:30 pm | No location | | Lunch Break [More Info] |
| 1:30 pm - 2:00 pm | Turret | | Generating Directed Tests Using VDK [More Info]
Praveen Wadikar, NVIDIA
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| 1:30 pm - 2:00 pm | Royal Ballroom | | Let Me Treat My SoC as IP; A Rewired Approach to SoC Level Elaboration Time Reduction in RTL Verification [More Info] |
| 1:30 pm - 2:15 pm | Grand Ballroom | | Achieving Highest Performance and Fastest Time-to-Results with IC Compiler II [More Info]
Neeraj Kaul, Synopsys
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| 1:30 pm - 2:15 pm | Jamavar | | PrimeTime Accuracy for Advanced Technology Nodes [More Info]
Sharath Narayana, Synopsys
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| 2:00 pm - 2:30 pm | Royal Ballroom | | Power Aware Blackbox Methodology for Optimized GLS/RTL/PARTL/PAGLS [More Info]
Bharath Kumar S, Qualcomm
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| 2:00 pm - 2:45 pm | Turret | | Building Smart SoCs: Using Virtual Prototyping for the Design and SoC Integration of Artificial Intelligence Accelerators [More Info]
Shripad Deshpande, Synopsys
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| 2:15 pm - 2:45 pm | Grand Ballroom | | A Novel Approach Towards Closure of 10M+ Design with 700+ Macros Running at 700MHz Using a Hybrid of Hierarchical and Flat Implementation Flows [More Info]
Rakesh Kumar, NXP
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| 2:15 pm - 2:45 pm | Jamavar | | Effective Timing Closure of Multimillion Gate Design with Advance Usage of Primetime Clock Fix ECO Utility and its Results Statistics [More Info]
Milap Darji, Qualcomm
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| 2:30 pm - 3:15 pm | Royal Ballroom | | Ready, SoC, Go: Automated Testbench Generation and Protocol Performance Verification to Fast-track your SoC [More Info]
SatyaPriya Acharya, Synopsys
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| 2:45 pm - 3:15 pm | Turret | | Efficient Cut Through Buffer for Low Latency Ethernet Systems [More Info]
Sudharsanan Ramachandran, Texas Instruments
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| 2:45 pm - 3:15 pm | Grand Ballroom | | Implementing the Multi (Million/physical-hierarchy/complexity/requirements) [More Info]
Rajeev Singh, Mediatek
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| 2:45 pm - 3:15 pm | Jamavar | | Smarter Design Signoff with PT Hyperscale Auto-Partition & Distribution [More Info]
Anshuman Seth, NVIDIA
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| 3:15 pm - 3:30 pm | No location | | Tea Break [More Info] |
| 3:30 pm - 4:00 pm | Grand Ballroom | | Dynamic Power Optimization of a High Frequency CPU Floating Point Unit - A Case Study [More Info]
Vinay Shivakumar, AMD
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| 3:30 pm - 4:00 pm | Royal Ballroom | | Fortifying Verification Environment with Drivers and Responders to Enhance Quality and Reduce Time [More Info]
Ankur Raj, NXP
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| 3:30 pm - 4:15 pm | Turret | | Ethernet Time-Sensitive Networking for SoCs Powering Autonomous Driving [More Info]
Anil Pothireddy, Synopsys
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| 3:30 pm - 4:15 pm | Jamavar | | Signoff Power Analysis Driven PrimeTime ECO for Best PPA - Accelerated by Machine Learning [More Info]
Gauri Sankar Malla, Synopsys
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| 4:00 pm - 4:30 pm | Grand Ballroom | | Evolved Bias Enabled UPF Flow with Supply Sets [More Info]
Sareeka Nagargoje, Seagate
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| 4:00 pm - 4:30 pm | Royal Ballroom | | Using VERDI to Define Annotations and Review Comments to Exclusions for Coverage Closure [More Info]
Sravankumar Sreeram, Xilinx
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| 4:15 pm - 4:45 pm | Turret | | ARC HS47D for Real Time Automotive Object Detection and Tracking using 77GHz RADAR [More Info]
Srinivas Katuri, Ineda Systems
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| 4:15 pm - 4:45 pm | Jamavar | | Optimizing Parasitic Extraction and Smart Debug Methods to Drive Timing Closure for a Billion Net SoC in FinFET Nodes [More Info]
Anukul Rangarajan, Qualcomm
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| 4:30 pm - 5:00 pm | Royal Ballroom | | A Distinctive Approach to Measure Performance Using Verdi Performance Analyzer on SOC [More Info]
Dinesh Shah, NXP
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| 4:30 pm - 5:00 pm | Grand Ballroom | | Physical Feedthrough, Crosstool Hierarchy and its Imperatives [More Info] |
| 4:45 pm - 5:15 pm | Turret | | ARC EM based MCU Subsystem for Automotive Functional Safety Applications [More Info]
Yashwanth Nagaraja, Analog Devices
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| 4:45 pm - 5:15 pm | Jamavar | | PrimeTime Constraints Analyzer Based Flow for Optimizing the Constraints in Early Design Cycle [More Info] |
| 5:30 pm - 8:15 pm | Grand Ballroom | | SNUG Pub [More Info] |
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| 7:45 am - 3:00 pm | Jamavar | | Registration [More Info] |
| 9:00 am - 10:15 am | Grand Ballroom | | Keynote - Data Centric World, Opportunities and Innovation [More Info]
Pradeep Elamanchili, Vice President, Global ASIC Engineering, Western Digital
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| 10:30 am - 11:15 am | Turret | | Reckoning Zebu Runtime Performance on DPI Function Calls [More Info]
Piyush Kumar Gupta, Arm
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| 10:30 am - 11:30 am | Grand Ballroom | | Best Practices for High-Performance, Energy Efficient Implementations of the Latest Arm® Processors in 7-nanometer FinFET (7FF) Process Technology Using Synopsys Design Platform [More Info]
Deep Kanwar Singh Bhullar, Arm
Sandeep Jain, Synopsys
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| 10:30 am - 11:30 am | Royal Ballroom | | Comprehensive SDC-based Clock Domain Crossing Verification [More Info]
Ravindra Nibandhe, Synopsys
Rangarajan Govindan, Synopsys
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| 10:30 am - 11:30 am | Jamavar | | State-of-the-Art Variation Models Using Machine Learning Technology in SiliconSmart [More Info]
Nanda Gopal, Synopsys
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| 11:15 am - 12:00 pm | Turret | | Out-of-the-Box Prototyping Enabling Interactive Software Development [More Info]
Pradeep Kumar M P, Synopsys
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| 11:30 am - 12:00 pm | Grand Ballroom | | Advance Nodes a LEAP in Physical Domain with ICC2 on Automotive design PPA [More Info]
Anil Yadav, STMicroelectronics
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| 11:30 am - 12:00 pm | Royal Ballroom | | Clock Domain Crossing Verification of a Bidirectional I/O IP with Mesochronous Clocks [More Info] |
| 11:30 am - 12:00 pm | Jamavar | | Standard Cell Electromigration(EM) Characterization Using SiliconSmart [More Info]
Sai Chaitanya Guruvu, Qualcomm
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| 12:00 pm - 12:15 pm | Grand Ballroom | | Introduction to Machine Learning and Data Science in Digital Implementation [More Info] |
| 12:00 pm - 12:30 pm | Jamavar | | Challenges in Characterizing Mix-Signal IPs Using SiliconSmart [More Info]
Subhra Lahiri, Cypress Semiconductors
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| 12:00 pm - 12:30 pm | Royal Ballroom | | Complex Chips Waiver Management System Using SpyGlass [More Info]
Bhavesh Jeewani, Qualcomm
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| 12:00 pm - 12:30 pm | Turret | | Prototyping Lower Power Intent for System Validation [More Info]
Sharath Duraiswami, Synopsys
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| 12:15 pm - 12:45 pm | Grand Ballroom | | Machine Learning Driven Data Analytics in IC Design Implementation [More Info] |
| 12:30 pm - 1:30 pm | No location | | Lunch Break [More Info] |
| 1:30 pm - 1:45 pm | Turret | | Welcome Note [More Info] |
| 1:30 pm - 2:00 pm | Royal Ballroom | | Efficient and Faster Handling of RTL LINT using SpyGlass Turbo LINT in Multi-million Gate SOC's [More Info]
Ashish Kumar Gupta, Broadcom
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| 1:30 pm - 2:30 pm | Jamavar | | Accelerating Full Coverage and Functional Safety Verification of Mixed-Signal Designs Using CustomSim and VCS AMS [More Info]
Antony Fan, Synopsys
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| 1:30 pm - 2:30 pm | Grand Ballroom | | Design Compiler Recent Technology Enhancements, QoR Improvements & Roadmap [More Info]
Philip Issac, Synopsys
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| 1:45 pm - 2:30 pm | Turret | | ASM-GaN: Industry Standard GaN HEMT Compact Model for Power-Electronics and RF Applications [More Info]
Prof. Yogesh Chauhan, IIT Kanpur
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| 2:00 pm - 2:30 pm | Royal Ballroom | | UPF Pipe Cleaning Flow Through Customized Partial State Retention Verification Using VC LP TCL APIs [More Info]
Bijoy Gopal Nandy, Qualcomm
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| 2:30 pm - 3:00 pm | Jamavar | | Automation in Custom Compiler for Analog Matched Device Placements & Routing [More Info]
Damini Garg, STMicroelectronics
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| 2:30 pm - 3:00 pm | Grand Ballroom | | Distinguished Physical Synthesis on Advanced FinFET Technology for Demanding Automotive SoC [More Info]
Rahul Kheterpal, STMicroelectronics
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| 2:30 pm - 3:15 pm | Turret | | Modeling Variability in FinFETs: From Devices to Circuits [More Info]
Prof. Udayan Ganguly, IIT Bombay
Dr. Sushant Mittal, Applied Materials
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| 3:00 pm - 3:30 pm | Jamavar | | Complex AMS Design Techniques with Customized Circuit Integrity checks [More Info]
Karan Shah, Qualcomm
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| 3:00 pm - 3:30 pm | Grand Ballroom | | Resolving Formality Conflicts for Designs Having Incomplete/Partial Power Architecture in RTL [More Info]
Rakesh Kumar, NXP
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| 3:30 pm - 3:45 pm | No location | | Tea Break [More Info] |
| 3:45 pm - 4:15 pm | Grand Ballroom | | Accelerated Design Convergence using IC Compiler II [More Info]
Sreekrishna Ramaswamy, Qualcomm
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| 3:45 pm - 4:15 pm | Jamavar | | Increase Design Robustness and Meet Design Timelines using Fast Monte Carlo Techniques on Full Memory Designs using CustomSim [More Info]
Shishir Kumar, STMicroelectronics
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| 3:45 pm - 4:30 pm | Turret | | Development of SOI-CMOS Process at 180nm Node Challenges & opportunities [More Info]
H.S. Jatana, Semi-Conductor Laboratory, Department of Space
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| 4:15 pm - 4:45 pm | Jamavar | | Determining the Preferred Methodology for Timing Analysis and Signoff of Mixed Signal Circuits [More Info]
Krishnan-talkad Sukumar, AMD
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| 4:15 pm - 4:45 pm | Grand Ballroom | | Faster Design Closer with IC Validator in Design Signoff Physical Verification Methodology [More Info]
Chandrashekhar Kukade, Juniper
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| 4:30 pm - 5:15 pm | Turret | | TD3.2: Application of TCAD in Design and Reliability of GaN and Si Power Transistors [More Info]
Dr. Mayank Shrivastava, IISc
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| 4:45 pm - 5:15 pm | Grand Ballroom | | Extreme Physical Verification Productivity Gains [More Info]
Anand Veerasangaiah, Synopsys
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| 5:15 pm - 5:45 pm | Grand Ballroom | | Awards [More Info] |
