SNUG India 2018

July 11, 2018 - July 12, 2018

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Preliminary Agenda

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Academia AMS
General Sessions IC Design: Signoff
IC Design: Test IC Implementation
IC Verification Networking Opportunities
Systems & IP Verification Hardware

July 11, 2018
7:30 am - 5:00 pmJamavar
Registration [More Info]
9:00 am - 10:15 amGrand Ballroom
Keynote - At the Heart of Impact [More Info]
Dr. Aart de Geus, Chairman & co-CEO, Synopsys
10:30 am - 11:00 amTurret
Next Generation Safety Focused Testing [More Info]
Pramod Notiyath, Synopsys
10:30 am - 11:30 amRoyal Ballroom
VC Formal Apps Expansion: Security, X-Prop and Registers Verification [More Info]
Sanjana Bhattacharya, Synopsys
10:30 am - 11:45 amGrand Ballroom
Extending the Frontiers of Digital Design with Synopsys Fusion Technologies [More Info]
Neeraj Kaul, Synopsys
Sanjay Bali, Synopsys
11:00 am - 11:30 amTurret
Reducing Design Turn Around Time & Test ECO's using SpyGlass RTL DFT Checks [More Info]
Sanjoy Nanda, Qualcomm
11:30 am - 12:00 pmRoyal Ballroom
Above and Beyond: Enable Shift-Left in Datapath Designs Using Design Exercise and RTL [More Info]
11:30 am - 12:00 pmTurret
UPF AWARE Scan Construction [More Info]
11:45 am - 12:15 pmGrand Ballroom
A Comprehensive Strategy to Resolve Methodology Issues for High-Performance ASIC's in 7nm [More Info]
Biswajit Maity, Broadcom
11:45 am - 12:15 pmJamavar
Tips and Tricks to Fix hold on 100% Utilized Regions of High Frequency Designs [More Info]
Gurjot Singh Bakhshi, NXP
12:00 pm - 12:30 pmTurret
Accelerating LOES Timing Closure on a High Performance Multimillion SoC [More Info]
Mahesh Rawal, Broadcom
12:00 pm - 12:45 pmRoyal Ballroom
Using Machine Learning to Improve Overall Verification Engineering Productivity, Quality, and Cost - Synopsys Case Studies [More Info]
Arun Venkatachar, Synopsys
12:15 pm - 12:45 pmJamavar
Effective Constraints Analysis for High Silicon Yield and Improved Implementation QoR [More Info]
Satyanarayana Medarametla, AMD
Raghu Pattipati, AMD
Payal Agarwal, AMD
Tejesh Ejanthkar, AMD
12:15 pm - 12:45 pmGrand Ballroom
Routing Convergence for High Performance Designs at Advanced Technology Nodes [More Info]
Shanmugapriya Murugesan, AMD
12:30 pm - 1:30 pmNo location
Lunch Break [More Info]
1:30 pm - 2:00 pmTurret
Generating Directed Tests Using VDK [More Info]
Praveen Wadikar, NVIDIA
1:30 pm - 2:00 pmRoyal Ballroom
Let Me Treat My SoC as IP; A Rewired Approach to SoC Level Elaboration Time Reduction in RTL Verification [More Info]
1:30 pm - 2:15 pmGrand Ballroom
Achieving Highest Performance and Fastest Time-to-Results with IC Compiler II [More Info]
Neeraj Kaul, Synopsys
1:30 pm - 2:15 pmJamavar
PrimeTime Accuracy for Advanced Technology Nodes [More Info]
Sharath Narayana, Synopsys
2:00 pm - 2:30 pmRoyal Ballroom
Power Aware Blackbox Methodology for Optimized GLS/RTL/PARTL/PAGLS [More Info]
Bharath Kumar S, Qualcomm
2:00 pm - 2:45 pmTurret
Building Smart SoCs: Using Virtual Prototyping for the Design and SoC Integration of Artificial Intelligence Accelerators [More Info]
Shripad Deshpande, Synopsys
2:15 pm - 2:45 pmGrand Ballroom
A Novel Approach Towards Closure of 10M+ Design with 700+ Macros Running at 700MHz Using a Hybrid of Hierarchical and Flat Implementation Flows [More Info]
Rakesh Kumar, NXP
2:15 pm - 2:45 pmJamavar
Effective Timing Closure of Multimillion Gate Design with Advance Usage of Primetime Clock Fix ECO Utility and its Results Statistics [More Info]
Milap Darji, Qualcomm
2:30 pm - 3:15 pmRoyal Ballroom
Ready, SoC, Go: Automated Testbench Generation and Protocol Performance Verification to Fast-track your SoC [More Info]
SatyaPriya Acharya, Synopsys
2:45 pm - 3:15 pmTurret
Efficient Cut Through Buffer for Low Latency Ethernet Systems [More Info]
Sudharsanan Ramachandran, Texas Instruments
2:45 pm - 3:15 pmGrand Ballroom
Implementing the Multi (Million/physical-hierarchy/complexity/requirements) [More Info]
Rajeev Singh, Mediatek
2:45 pm - 3:15 pmJamavar
Smarter Design Signoff with PT Hyperscale Auto-Partition & Distribution [More Info]
Anshuman Seth, NVIDIA
3:15 pm - 3:30 pmNo location
Tea Break [More Info]
3:30 pm - 4:00 pmGrand Ballroom
Dynamic Power Optimization of a High Frequency CPU Floating Point Unit - A Case Study [More Info]
Vinay Shivakumar, AMD
3:30 pm - 4:00 pmRoyal Ballroom
Fortifying Verification Environment with Drivers and Responders to Enhance Quality and Reduce Time [More Info]
Ankur Raj, NXP
3:30 pm - 4:15 pmTurret
Ethernet Time-Sensitive Networking for SoCs Powering Autonomous Driving [More Info]
Anil Pothireddy, Synopsys
3:30 pm - 4:15 pmJamavar
Signoff Power Analysis Driven PrimeTime ECO for Best PPA - Accelerated by Machine Learning [More Info]
Gauri Sankar Malla, Synopsys
4:00 pm - 4:30 pmGrand Ballroom
Evolved Bias Enabled UPF Flow with Supply Sets [More Info]
Sareeka Nagargoje, Seagate
4:00 pm - 4:30 pmRoyal Ballroom
Using VERDI to Define Annotations and Review Comments to Exclusions for Coverage Closure [More Info]
Sravankumar Sreeram, Xilinx
4:15 pm - 4:45 pmTurret
ARC HS47D for Real Time Automotive Object Detection and Tracking using 77GHz RADAR [More Info]
Srinivas Katuri, Ineda Systems
4:15 pm - 4:45 pmJamavar
Optimizing Parasitic Extraction and Smart Debug Methods to Drive Timing Closure for a Billion Net SoC in FinFET Nodes [More Info]
Anukul Rangarajan, Qualcomm
4:30 pm - 5:00 pmRoyal Ballroom
A Distinctive Approach to Measure Performance Using Verdi Performance Analyzer on SOC [More Info]
Dinesh Shah, NXP
4:30 pm - 5:00 pmGrand Ballroom
Physical Feedthrough, Crosstool Hierarchy and its Imperatives [More Info]
4:45 pm - 5:15 pmTurret
ARC EM based MCU Subsystem for Automotive Functional Safety Applications [More Info]
Yashwanth Nagaraja, Analog Devices
4:45 pm - 5:15 pmJamavar
PrimeTime Constraints Analyzer Based Flow for Optimizing the Constraints in Early Design Cycle [More Info]
5:30 pm - 8:15 pmGrand Ballroom
SNUG Pub [More Info]
July 12, 2018
7:45 am - 3:00 pmJamavar
Registration [More Info]
9:00 am - 10:15 amGrand Ballroom
Keynote - Data Centric World, Opportunities and Innovation [More Info]
Pradeep Elamanchili, Vice President, Global ASIC Engineering, Western Digital
10:30 am - 11:15 amTurret
Reckoning Zebu Runtime Performance on DPI Function Calls [More Info]
Piyush Kumar Gupta, Arm
10:30 am - 11:30 amGrand Ballroom
Best Practices for High-Performance, Energy Efficient Implementations of the Latest Arm® Processors in 7-nanometer FinFET (7FF) Process Technology Using Synopsys Design Platform [More Info]
Deep Kanwar Singh Bhullar, Arm
Sandeep Jain, Synopsys
10:30 am - 11:30 amRoyal Ballroom
Comprehensive SDC-based Clock Domain Crossing Verification [More Info]
Ravindra Nibandhe, Synopsys
Rangarajan Govindan, Synopsys
10:30 am - 11:30 amJamavar
State-of-the-Art Variation Models Using Machine Learning Technology in SiliconSmart [More Info]
Nanda Gopal, Synopsys
11:15 am - 12:00 pmTurret
Out-of-the-Box Prototyping Enabling Interactive Software Development [More Info]
Pradeep Kumar M P, Synopsys
11:30 am - 12:00 pmGrand Ballroom
Advance Nodes a LEAP in Physical Domain with ICC2 on Automotive design PPA [More Info]
Anil Yadav, STMicroelectronics
11:30 am - 12:00 pmRoyal Ballroom
Clock Domain Crossing Verification of a Bidirectional I/O IP with Mesochronous Clocks [More Info]
11:30 am - 12:00 pmJamavar
Standard Cell Electromigration(EM) Characterization Using SiliconSmart [More Info]
Sai Chaitanya Guruvu, Qualcomm
12:00 pm - 12:15 pmGrand Ballroom
Introduction to Machine Learning and Data Science in Digital Implementation [More Info]
12:00 pm - 12:30 pmJamavar
Challenges in Characterizing Mix-Signal IPs Using SiliconSmart [More Info]
Subhra Lahiri, Cypress Semiconductors
12:00 pm - 12:30 pmRoyal Ballroom
Complex Chips Waiver Management System Using SpyGlass [More Info]
Bhavesh Jeewani, Qualcomm
12:00 pm - 12:30 pmTurret
Prototyping Lower Power Intent for System Validation [More Info]
Sharath Duraiswami, Synopsys
12:15 pm - 12:45 pmGrand Ballroom
Machine Learning Driven Data Analytics in IC Design Implementation [More Info]
12:30 pm - 1:30 pmNo location
Lunch Break [More Info]
1:30 pm - 1:45 pmTurret
Welcome Note [More Info]
1:30 pm - 2:00 pmRoyal Ballroom
Efficient and Faster Handling of RTL LINT using SpyGlass Turbo LINT in Multi-million Gate SOC's [More Info]
Ashish Kumar Gupta, Broadcom
1:30 pm - 2:30 pmJamavar
Accelerating Full Coverage and Functional Safety Verification of Mixed-Signal Designs Using CustomSim and VCS AMS [More Info]
Antony Fan, Synopsys
1:30 pm - 2:30 pmGrand Ballroom
Design Compiler Recent Technology Enhancements, QoR Improvements & Roadmap [More Info]
Philip Issac, Synopsys
1:45 pm - 2:30 pmTurret
ASM-GaN: Industry Standard GaN HEMT Compact Model for Power-Electronics and RF Applications [More Info]
Prof. Yogesh Chauhan, IIT Kanpur
2:00 pm - 2:30 pmRoyal Ballroom
UPF Pipe Cleaning Flow Through Customized Partial State Retention Verification Using VC LP TCL APIs [More Info]
Bijoy Gopal Nandy, Qualcomm
2:30 pm - 3:00 pmJamavar
Automation in Custom Compiler for Analog Matched Device Placements & Routing [More Info]
Damini Garg, STMicroelectronics
2:30 pm - 3:00 pmGrand Ballroom
Distinguished Physical Synthesis on Advanced FinFET Technology for Demanding Automotive SoC [More Info]
Rahul Kheterpal, STMicroelectronics
2:30 pm - 3:15 pmTurret
Modeling Variability in FinFETs: From Devices to Circuits [More Info]
Prof. Udayan Ganguly, IIT Bombay
Dr. Sushant Mittal, Applied Materials
3:00 pm - 3:30 pmJamavar
Complex AMS Design Techniques with Customized Circuit Integrity checks [More Info]
Karan Shah, Qualcomm
3:00 pm - 3:30 pmGrand Ballroom
Resolving Formality Conflicts for Designs Having Incomplete/Partial Power Architecture in RTL [More Info]
Rakesh Kumar, NXP
3:30 pm - 3:45 pmNo location
Tea Break [More Info]
3:45 pm - 4:15 pmGrand Ballroom
Accelerated Design Convergence using IC Compiler II [More Info]
Sreekrishna Ramaswamy, Qualcomm
3:45 pm - 4:15 pmJamavar
Increase Design Robustness and Meet Design Timelines using Fast Monte Carlo Techniques on Full Memory Designs using CustomSim [More Info]
Shishir Kumar, STMicroelectronics
3:45 pm - 4:30 pmTurret
Development of SOI-CMOS Process at 180nm Node Challenges & opportunities [More Info]
H.S. Jatana, Semi-Conductor Laboratory, Department of Space
4:15 pm - 4:45 pmJamavar
Determining the Preferred Methodology for Timing Analysis and Signoff of Mixed Signal Circuits [More Info]
Krishnan-talkad Sukumar, AMD
4:15 pm - 4:45 pmGrand Ballroom
Faster Design Closer with IC Validator in Design Signoff Physical Verification Methodology [More Info]
Chandrashekhar Kukade, Juniper
4:30 pm - 5:15 pmTurret
TD3.2: Application of TCAD in Design and Reliability of GaN and Si Power Transistors [More Info]
Dr. Mayank Shrivastava, IISc
4:45 pm - 5:15 pmGrand Ballroom
Extreme Physical Verification Productivity Gains [More Info]
Anand Veerasangaiah, Synopsys
5:15 pm - 5:45 pmGrand Ballroom
Awards [More Info]
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