| 7:45 am - 6:30 pm | Promenade | | Registration [More Info] |
| 9:15 am - 10:30 am | Grand Ballroom | | Keynote: Evolution of Trust in a Changing Ecosystem [More Info]
Speaker: Dr. Chi-Foon Chan, President and co-Chief Executive Officer, Synopsys
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| 10:45 am - 11:30 am | Middlesex | | Auditing the UVM Resource Database [More Info]
Nitin Prakash, Cavium
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| 10:45 am - 11:30 am | Wayland | | For the First Time Ever, We Urge You to Trunk and Drive [More Info] |
| 10:45 am - 11:30 am | Ashland | | Synopsys Machine Learning with a PrimeTime ECO Tutorial [More Info]
Joe Walston, Synopsys
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| 11:30 am - 12:15 pm | Wayland | | Design Migration: Making Your Intention Known [More Info] |
| 11:30 am - 12:15 pm | Ashland | | PrimeTime 2017.12 Overview and Reporting Runtime and Productivity Improvements [More Info]
Bob Grozier, Synopsys
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| 11:30 am - 12:15 pm | Middlesex | | Wait Management in UVM 1.2 RAL: Cutting Sequence Delay the No-Wait Way [More Info]
Steven K. Sherman, Verification Engineer, Advanced Micro Devices
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| 12:15 pm - 1:30 pm | Grand Ballroom | | Networking Lunch |
| 1:30 pm - 2:05 pm | Middlesex | | Stimulus Driven Methodology for Emulation Based Software and Hardware Verification of AMD x86 Microprocessor Designs [More Info]
Oleg Petlin, Advanced Micro Devices
Adithya Yalavarti, Senior Member of Technical Staff, Advanced Micro Devices
John Zaghi, Synopsys
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| 1:30 pm - 2:10 pm | Ashland | | Design Compiler Update and Advanced Node Support [More Info]
Bob Wiegand, Synopsys
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| 1:30 pm - 2:10 pm | Wayland | | Optimizing Hierarchical Design Through Abstract Modeling [More Info] |
| 1:30 pm - 2:10 pm | Concord | | Using SpyGlass DFT ADV & DFTMAX Physical-Aware Test Point Insertion to Increase ATPG Efficiency [More Info]
Sounil Biswas, Cavium
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| 2:05 pm - 2:40 pm | Middlesex | | TCP/IP Socket Based Communication for SystemVerilog Simulation [More Info]
Victor Besyakov, Asic Verification Consultant, IC Verimeter, BTA Design Services
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| 2:10 pm - 2:50 pm | Wayland | | Achieving Optimal Placement of Pipeline Registers Added During Full Chip Floorplanning [More Info]
Aziz Mohammed, Senior Member of Technical Staff, Advanced Micro Devices
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| 2:10 pm - 2:50 pm | Ashland | | Minimizing Runtime and Debug of Large Designs [More Info]
Tom Wilderotter, Synopsys
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| 2:10 pm - 2:50 pm | Concord | | RAM Shadow Fault ATPG for Memory-intensive SoCs [More Info] |
| 2:40 pm - 3:15 pm | Middlesex | | Using (auto-generated) SystemVerilog Constraints to Test (auto-generated) C Models [More Info]
Henry Cox, Mediatek
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| 2:50 pm - 3:30 pm | Ashland | | Automated Synthesis Script Generation [More Info]
Timothy Howe, Senior Staff Design Engineer, GLOBALFOUNDRIES
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| 2:50 pm - 3:30 pm | Wayland | | Block Level Floorplan Debug with IC Compiler II [More Info]
Pete Churchill, Synopsys
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| 2:50 pm - 3:30 pm | Concord | | Managing the Cost and Complexity of Test from Early RTL Test Analysis through Faster, More Efficient ATPG [More Info]
Don Skinner, Synopsys
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| 3:15 pm - 3:30 pm | Middlesex | | Improving Simulation Throughput with Fine-Grained Parallelism (FGP) [More Info]
Joseph Basmaji, Synopsys
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| 3:45 pm - 4:30 pm | Middlesex | | Architectural Formal Verification: A 3-Step Guide [More Info]
Kamal Sekhon, Oski Technology
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| 3:45 pm - 4:30 pm | Concord | | Comprehensive SDC-based Clock Domain Crossing Verification [More Info]
Greg Milano, Synopsys
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| 3:45 pm - 4:30 pm | Ashland | | Formality Best Practices and Technology Update [More Info]
Steve Lamb, Synopsys
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| 3:45 pm - 4:30 pm | Wayland | | Synopsys Machine Learning with an Arm Case Study [More Info]
Joe Walston, Synopsys
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| 4:30 pm - 5:15 pm | Wayland | | Achieving Best QoR and Fastest TAT with Synopsys' Design Platform [More Info]
Arvind Narayanan, Synopsys
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| 4:30 pm - 5:15 pm | Concord | | Introduction to Reset Domain Crossings [More Info]
Greg Milano, Synopsys
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| 4:30 pm - 5:15 pm | Middlesex | | Ready, SoC, Go: Automated Testbench Generation and Protocol Performance Verification to Fast-track SoCs [More Info]
Bernie DeLay, Synopsys
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| 4:30 pm - 5:15 pm | Ashland | | What's New With PrimeTime PX [More Info]
John Geremia, Synopsys
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| 5:15 pm - 7:15 pm | Grand Ballroom | | SNUG Pub and Awards Ceremony [More Info] |
