Automotive | |||
Thursday, October 19, 2017 | |||
10:30 am - 11:10 am | 412 | Timing Closure of High PPA Automotive Designs using LVF Libraries [More Info] Shruti Saxena, Design Engineer, NXP Semiconductors Savithri Sundareswaran, NXP Semiconductors Danny Bradley, Synopsys | |
11:10 am - 11:50 am | 412 | Meeting IP Requirements of ADAS Automotive SoCs [More Info] Ron DiGiuseppe, Synopsys | |
11:50 am - 12:30 pm | 412 | Automotive Panel: Safety Critical Automotive Designs, What's The Difference? [More Info] Anis Jarrar, NXP Semiconductors Fergus Casey, Synopsys Frank Noha, NVIDIA Jeff Hutton, Synopsys | |
Backend Implementation | |||
Thursday, October 19, 2017 | |||
10:30 am - 11:50 am | Salon E | Best Practices for High-Performance, Energy Efficient Implementations of the Latest Arm® Processors in 16-nanometer FinFET Compact (16FFC) Process Technology Using Synopsys Design Platform [More Info] Joe Walston, Synopsys | |
11:50 am - 12:30 pm | Salon E | Run-Time Benefit by Design Reuse [More Info] Shrikant Kulkarni, Sr. Design Engineer, Advanced Micro Devices | |
1:30 pm - 2:10 pm | Salon E | MS-CTS Incorporated with CCD for Mobile CPU Core Using IC Compiler II [More Info] Hosoon Shin, Staff Engineer II, LG Electronics | |
2:10 pm - 3:30 pm | Salon E | Mastering the Challenges of 7 nm Design for Best-in-Class QoR with IC Compiler II [More Info] Mark Richards, Synopsys Paul Cole, Synopsys | |
3:45 pm - 4:25 pm | Salon E | Top Down Timing Budgeting for Hierarchical SoC Designs [More Info] | |
4:25 pm - 5:15 pm | Salon E | IC Compiler II GUI, A Hands on Tutorial on How to Use IC Compiler II's Route Editor to Interactively Route and Edit Critical Signals Before Detail Route [More Info] John Griner, Synopsys | |
Frontend Implementation | |||
Thursday, October 19, 2017 | |||
10:30 am - 11:10 am | Salon D | Improving Accuracy and Turnaround-Time for Block-Level Leakage Optimizations Using Binary Context [More Info] Erik Gonzalez, Advanced Micro Devices | |
11:10 am - 11:50 am | Salon D | The Next Generation of HyperScale – Speed, Resource Efficiency and Added Flexibility [More Info] Jenny Pencis, Senior Staff Applications Consultant, Synopsys | |
11:50 am - 12:30 pm | Salon D | PrimeTime ECO – Introducing Clock ECO [More Info] Troy Epperly, Synopsys | |
1:30 pm - 2:10 pm | Salon D | Early Congestion Analysis and RTL Fix [More Info] Chris Meng, PMTS, Advanced Micro Devices | |
2:10 pm - 2:50 pm | Salon D | Principles of Low Power Design using UPF [More Info] David Yatim, Synopsys | |
2:50 pm - 3:30 pm | Salon D | Design Compiler 2017.09 Update [More Info] Jim Argraves, Synopsys | |
3:45 pm - 4:30 pm | Salon D | What’s New for UPF 3.0 on the Galaxy Platform [More Info] John Geremia, Synopsys | |
4:30 pm - 5:15 pm | Salon D | A “Completely Cool’ Case Study - Synopsys Low Power Frontend Implementation [More Info] Michael Montana, Synopsys | |
Full Custom Implementation | |||
Thursday, October 19, 2017 | |||
1:30 pm - 2:10 pm | 410 | Expanding On Traditional Cosim Methodologies with VCS AMS (CustomSim-VCS) [More Info] John Brennan, Principal Engineer, Cavium | |
2:10 pm - 2:50 pm | 410 | An STA Methodology for Timing a Double Pumped 6T SRAM Macro using NanoTime [More Info] Ryan Freese, SMTS Design Engineer, Advanced Micro Devices | |
2:50 pm - 3:30 pm | 410 | Self-Heat Aware Electro-Migration (EM) Simulation and Analysis with CustomSim™ for FinFET Devices and Smaller Geometries [More Info] Haran Thanikasalam, Synopsys | |
3:45 pm - 4:30 pm | 410 | Rapid Layout of 7nm Custom Digital Designs using Custom Compiler [More Info] Kelly Burleson, Synopsys | |
4:30 pm - 5:15 pm | 410 | ESP for Library Verification [More Info] Rick Eversole, Synopsys | |
General Sessions | |||
Thursday, October 19, 2017 | |||
8:00 am - 8:45 am | Foyer | Registration and Breakfast | |
9:00 am - 9:15 am | Governor's Ballroom | Welcome to SNUG Austin | |
9:15 am - 10:15 am | Governor's Ballroom | Keynote - Smart, Secure Everything from Silicon to Software [More Info] Sassine Ghazi, Synopsys | |
10:15 am - 10:30 am | Foyer | Break | |
12:30 pm - 1:30 pm | Governor's Ballroom | Lunch | |
3:30 pm - 3:45 pm | Foyer | Break | |
5:15 pm - 7:00 pm | Governor's Ballroom | SNUG Pub | |
Test | |||
Thursday, October 19, 2017 | |||
1:30 pm - 2:10 pm | 412 | Pattern Translation and Verification of DFTMAX Ultra Patterns in Hierarchical ATPG [More Info] Neil Hao, DFX Manager, Advanced Micro Devices | |
2:10 pm - 2:50 pm | 412 | Cell-Aware Test for Lower DPPM and Faster Silicon Yield Ramp with Diagnostics [More Info] Brian Archer, Synopsys Steve Palosh, Synopsys | |
2:50 pm - 3:30 pm | 412 | SpyGlass® DFT ADV: High Testability, SoC Connectivity, Functional Safety and Reliability [More Info] Al Joseph, Synopsys | |
3:45 pm - 4:30 pm | 412 | Scoring Big Points (Coverage, Cost, QoR) With Test Points. A DFT Hat Trick! [More Info] Don Dattani, Silicon Director, Cognitive Systems | |
4:30 pm - 5:15 pm | 412 | Meet Your Test Quality and Cost Goals with Unprecedented Speed [More Info] Brad MacMonagle, Senior Staff Application Consultant, Synopsys | |
User Content Reviewed by the Technical Committee | |||
Thursday, October 19, 2017 | |||
10:30 am - 11:10 am | Salon D | Improving Accuracy and Turnaround-Time for Block-Level Leakage Optimizations Using Binary Context [More Info] Erik Gonzalez, Advanced Micro Devices | |
10:30 am - 11:10 am | 412 | Timing Closure of High PPA Automotive Designs using LVF Libraries [More Info] Shruti Saxena, Design Engineer, NXP Semiconductors Savithri Sundareswaran, NXP Semiconductors Danny Bradley, Synopsys | |
10:30 am - 11:10 am | 406 | Verification Prowess with the UVM Harness [More Info] Jeff Vance, Design Verification Engineer, Verilab Jeffrey Montesano, Senior Verification Consultant, Verilab | |
11:10 am - 11:50 am | 406 | Formal Verification of a Pipelined Multiplier Design for a High Performance Processor Core [More Info] Pratyush Jain, Sr Design Engineer, AMD | |
11:50 am - 12:30 pm | 406 | Fast and Furious: A 8x Runtime Performance [More Info] Sujit Shah, Senior Verification Engineer, Centaur Technology, Inc Weihua Han, Applications Engineer, Synopsys | |
11:50 am - 12:30 pm | Salon E | Run-Time Benefit by Design Reuse [More Info] Shrikant Kulkarni, Sr. Design Engineer, Advanced Micro Devices | |
1:30 pm - 2:10 pm | Salon D | Early Congestion Analysis and RTL Fix [More Info] Chris Meng, PMTS, Advanced Micro Devices | |
1:30 pm - 2:10 pm | 410 | Expanding On Traditional Cosim Methodologies with VCS AMS (CustomSim-VCS) [More Info] John Brennan, Principal Engineer, Cavium | |
1:30 pm - 2:10 pm | Salon E | MS-CTS Incorporated with CCD for Mobile CPU Core Using IC Compiler II [More Info] Hosoon Shin, Staff Engineer II, LG Electronics | |
1:30 pm - 2:10 pm | 412 | Pattern Translation and Verification of DFTMAX Ultra Patterns in Hierarchical ATPG [More Info] Neil Hao, DFX Manager, Advanced Micro Devices | |
1:30 pm - 2:10 pm | 408 | SoC Connectivity Checking with VC Formal Using a Domain Specific Language [More Info] Lars Viklund, ASIC Verification Lead, Axis Communications | |
2:10 pm - 2:50 pm | 410 | An STA Methodology for Timing a Double Pumped 6T SRAM Macro using NanoTime [More Info] Ryan Freese, SMTS Design Engineer, Advanced Micro Devices | |
2:10 pm - 2:50 pm | 408 | FCA (Formal Coverage Analyzer): Using Formal Unreachability Analysis to Accelerate Toggle Coverage Closure [More Info] Jimmy Thayil, SoC Verification Engineer, NXP Semiconductors Jing Huang, Senior Engineer, NXP Semiconductors | |
2:10 pm - 2:50 pm | 406 | SoC Verification Challenges Eased with Reusable Test Suites and Customizable Performance Analyzers [More Info] Aravind Prakash, NXP Semiconductors Hema Thyagarajan, NXP Semiconductors | |
2:50 pm - 3:30 pm | 406 | Are you Planning to Fail or Failing to Plan? [More Info] Aditya Musunuri, NXP Semiconductors Aditya Musunuri, NXP | |
3:45 pm - 4:30 pm | 408 | Gate Verification: Gateway to Better Results! [More Info] Vaibhav Kumar, Design Engineer, NXP Semiconductors | |
3:45 pm - 4:25 pm | Salon E | Top Down Timing Budgeting for Hierarchical SoC Designs [More Info] | |
4:30 pm - 5:15 pm | 406 | A Unique Approach for SoC Reset Connectivity Verification [More Info] Ratika Goyal, NXP Semiconductors | |
Verification Continuum I | |||
Thursday, October 19, 2017 | |||
10:30 am - 11:10 am | 406 | Verification Prowess with the UVM Harness [More Info] Jeff Vance, Design Verification Engineer, Verilab Jeffrey Montesano, Senior Verification Consultant, Verilab | |
11:10 am - 11:50 am | 406 | Formal Verification of a Pipelined Multiplier Design for a High Performance Processor Core [More Info] Pratyush Jain, Sr Design Engineer, AMD | |
11:50 am - 12:30 pm | 406 | Fast and Furious: A 8x Runtime Performance [More Info] Sujit Shah, Senior Verification Engineer, Centaur Technology, Inc Weihua Han, Applications Engineer, Synopsys | |
1:30 pm - 2:10 pm | 406 | Boosting Debug Productivity - Practical Applications of Verdi Debug Innovations [More Info] Alex Wakefield, Synopsys | |
2:10 pm - 2:50 pm | 406 | SoC Verification Challenges Eased with Reusable Test Suites and Customizable Performance Analyzers [More Info] Aravind Prakash, NXP Semiconductors Hema Thyagarajan, NXP Semiconductors | |
2:50 pm - 3:30 pm | 406 | Are you Planning to Fail or Failing to Plan? [More Info] Aditya Musunuri, NXP Semiconductors Aditya Musunuri, NXP | |
3:45 pm - 4:30 pm | 406 | SpyGlass Reset Domain Crossing Analysis [More Info] Russ Roan, Synopsys | |
4:30 pm - 5:15 pm | 406 | A Unique Approach for SoC Reset Connectivity Verification [More Info] Ratika Goyal, NXP Semiconductors | |
Verification Continuum II (Emulation/Prototyping) | |||
Thursday, October 19, 2017 | |||
1:30 pm - 2:10 pm | 408 | SoC Connectivity Checking with VC Formal Using a Domain Specific Language [More Info] Lars Viklund, ASIC Verification Lead, Axis Communications | |
2:10 pm - 2:50 pm | 408 | FCA (Formal Coverage Analyzer): Using Formal Unreachability Analysis to Accelerate Toggle Coverage Closure [More Info] Jimmy Thayil, SoC Verification Engineer, NXP Semiconductors Jing Huang, Senior Engineer, NXP Semiconductors | |
2:50 pm - 3:30 pm | 408 | Increase Your Verification Productivity With VC Formal [More Info] Tareq Altakrouri, Synopsys | |
3:45 pm - 4:30 pm | 408 | Gate Verification: Gateway to Better Results! [More Info] Vaibhav Kumar, Design Engineer, NXP Semiconductors | |
4:30 pm - 5:15 pm | 408 | A “Completely Cool” Case Study – Synopsys Low Power Verification [More Info] Tushar Parikh, Senior Staff Engineer, Synopsys | |
Verification Continuum III (FPGA & Prototyping) | |||
Thursday, October 19, 2017 | |||
10:30 am - 11:10 am | 410 | Enabling High Reliability and Functional Safety for FPGA Based Hardware Design [More Info] Carl Cleaver, Staff Applications Consultant, Synopsys | |
11:10 am - 11:50 am | 410 | Advanced Debug Techniques for HAPS Prototyping [More Info] Bob Efram, Staff Applications Consultant, Synopsys | |
11:50 am - 12:30 pm | 410 | GPU Prototyping with HAPS [More Info] Kris Dobecki, Applications Consultant, Synopsys |