| Custom & AMS | |||
| Thursday, June 22, 2017 | |||
| 10:45 - 11:15 | Cervin | An Configurable V/I Source/Probe Testbench Component for AMS [More Info] Peter Grove, Dialog SemiConductor Ltd. | |
| 11:15 - 11:45 | Cervin | 40nm Test Chip Verification: Co-simulation Methodology with Digital-On-Top Approach Based on VCS AMS (CustomSim-VCS) [More Info] Enrico Castaldo, STMicroelectronics | |
| 11:45 - 12:15 | Cervin | Custom Compiler Mixed Flow Demo [More Info] Fouad Bissane, Synopsys | |
| 13:30 - 14:00 | Cervin | DDR System Simulation/Optimization of an Integrated MultiPHY IP [More Info] Déborah Cogoni, STMicroelectronics | |
| 14:00 - 14:30 | Cervin | STMicroelectronics-LIRMM: An Advanced Diagnosis Flow Using CustomSim for SRAMs [More Info] Tien-Phu HO, STMicroelectronics/LIRMM Patrice Loth, Synopsys | |
| 14:30 - 15:00 | Cervin | Custom Compiler Customization for ST Design Flows [More Info] Sébastien Mathieu, STMicroelectronics Eric Nercessian, STMicroelectronics | |
| 15:30 - 17:00 | Cervin | Rapid Layout of 7nm Custom Digital Designs Using Custom Compiler [More Info] Damian Roberts, Synopsys | |
| Design for Test & Pattern Generation | |||
| Thursday, June 22, 2017 | |||
| 10:45 - 11:15 | Kilimandjaro 1 | IP Testing Based on DFT Wrapping by DFTMAX® and Pattern Porting by TetraMAX® Utility (STILGen) [More Info] Fabio Mazza, STMicroelectronics | |
| 11:15 - 11:45 | Kilimandjaro 1 | DFTMax to DFTMax Ultra Transition in Microcontroller Designs [More Info] Marc Beaujoin, STMicroelectronics Cédric Escallier, STMicroelectronics | |
| 11:45 - 12:15 | Kilimandjaro 1 | TetraMax II ATPG [More Info] Philippe Rossant, Synopsys | |
| 13:30 - 14:00 | Kilimandjaro 1 | Accelerating Silicon Diagnosis Using a Cell-Aware Flow [More Info] Nelly Feldman, STMicroelectronics | |
| 14:00 - 14:30 | Kilimandjaro 1 | ZOIX Evaluation in a STM32 Microcontroller [More Info] Martino Quattrocchi, STMicroelectronics | |
| 14:30 - 15:00 | Kilimandjaro 1 | Improve Fault Coverage with ZOIX Fault Simulation [More Info] Jean-Marc Forey, Synopsys | |
| 15:30 - 16:30 | Kilimandjaro 1 | SpyGlass® DFT ADV: High Testability, SoC Connectivity, Functional Safety and Reliability [More Info] Jean-Pierre Popieul, Synopsys | |
| 16:30 - 17:00 | Kilimandjaro 1 | Physically Aware Test Points [More Info] Pierre Duclos, Synopsys | |
| Frontend Implementation | |||
| Thursday, June 22, 2017 | |||
| 10:45 - 11:15 | Mont-Blanc 1 | Improving Flow Convergence Through Integrated Clock Gating Constraint Management [More Info] Choukri Saidi, STMicroelectronics | |
| 11:15 - 12:15 | Mont-Blanc 1 | Galaxy RTL: Design Compiler Family M-2016.12 Update [More Info] Ludovic Pinon, Synopsys | |
| 13:30 - 14:00 | Mont-Blanc 1 | The Early Power Estimation Lottery: Increasing the Accuracy of Results in Order to Pick the Winning Number [More Info] Alessandro Nale, Nokia | |
| 14:00 - 15:00 | Mont-Blanc 1 | PrimeTime PX Power and Reliability Analysis of Multi-voltage Designs Through the Flow [More Info] Maria Tovey, Synopsys | |
| 15:30 - 16:00 | Mont-Blanc 1 | VC-LP : Not just for chips! [More Info] Ben Kerr, Toshiba America Electronic Components | |
| 16:00 - 17:00 | Mont-Blanc 1 | A “Completely Cool” Case study – Bitcoin Low Power Flow & Methodology – Implementation [More Info] Pascal Coffin, Synopsys | |
| General Sessions | |||
| Thursday, June 22, 2017 | |||
| 08:30 - 09:30 | Atrium | Breakfast | |
| 08:30 - 18:00 | Atrium | Registration | |
| 09:30 - 10:30 | Auditorium | Keynote - From Silicon to Software, Smartness Is Everything [More Info] Dr. Antun Domic, Executive Vice President and General Manager, Design Group, Synopsys | |
| 12:15 - 13:30 | Atrium | Networking Lunch | |
| 17:00 - 18:00 | Atrium | Awards and Refreshments | |
| Physical Design & Signoff | |||
| Thursday, June 22, 2017 | |||
| 10:45 - 11:15 | Mont-Blanc 3 | [ST Microelectronics - TIMA] Tool Chain for Early Digital Design Failure Rate Estimation & Workload Aged Timing Analysis [More Info] Ajith Sivadasan, STMicroelectronics | |
| 11:15 - 11:45 | Mont-Blanc 3 | Methodology to Sign Off Custom Layout Modifications with Static Timing Analysis for Nand Flash Type Memory Designs [More Info] Domenico Tuzi, Micron Semiconductor | |
| 11:45 - 12:15 | Mont-Blanc 3 | Advanced Techniques to Reduce the Crosstalk Pessimism in the PrimeTime SI Timing Analysis [More Info] Patrick Bougant, STMicroelectronics | |
| 13:30 - 14:30 | Mont-Blanc 3 | IC Compiler II 2016.12 Update [More Info] Hervé Raffard, Synopsys | |
| 14:30 - 15:00 | Mont-Blanc 3 | Pipeline Register Planning [More Info] Gaspard Thaller, Synopsys | |
| 15:30 - 16:00 | Mont-Blanc 3 | Faster Timing Closure with Useful Skew using PrimeTime Clock ECO [More Info] Tarun Chawla, STMicroelectronics | |
| 16:00 - 16:30 | Mont-Blanc 3 | Galaxy Incremental Signoff ECO Flow [More Info] Gaspard Thaller, Synopsys | |
| 16:30 - 17:00 | Mont-Blanc 3 | Accelerating ECO Implementation Using Formality Ultra [More Info] Eric Zann, Synopsys | |
| User Content Reviewed by the Technical Committee | |||
| Thursday, June 22, 2017 | |||
| 10:45 - 11:15 | Mont-Blanc 3 | [ST Microelectronics - TIMA] Tool Chain for Early Digital Design Failure Rate Estimation & Workload Aged Timing Analysis [More Info] Ajith Sivadasan, STMicroelectronics | |
| 10:45 - 11:15 | Cervin | An Configurable V/I Source/Probe Testbench Component for AMS [More Info] Peter Grove, Dialog SemiConductor Ltd. | |
| 10:45 - 11:15 | Mont-Blanc 1 | Improving Flow Convergence Through Integrated Clock Gating Constraint Management [More Info] Choukri Saidi, STMicroelectronics | |
| 10:45 - 11:15 | Kilimandjaro 1 | IP Testing Based on DFT Wrapping by DFTMAX® and Pattern Porting by TetraMAX® Utility (STILGen) [More Info] Fabio Mazza, STMicroelectronics | |
| 10:45 - 11:15 | Kilimandjaro 3 | Performance Analysis of an ADAS System with Synopsys Platform Architect MCO [More Info] | |
| 11:15 - 11:45 | Cervin | 40nm Test Chip Verification: Co-simulation Methodology with Digital-On-Top Approach Based on VCS AMS (CustomSim-VCS) [More Info] Enrico Castaldo, STMicroelectronics | |
| 11:15 - 11:45 | Kilimandjaro 1 | DFTMax to DFTMax Ultra Transition in Microcontroller Designs [More Info] Marc Beaujoin, STMicroelectronics Cédric Escallier, STMicroelectronics | |
| 11:15 - 11:45 | Mont-Blanc 3 | Methodology to Sign Off Custom Layout Modifications with Static Timing Analysis for Nand Flash Type Memory Designs [More Info] Domenico Tuzi, Micron Semiconductor | |
| 11:15 - 11:45 | Kilimandjaro 3 | Platform Architect for HPC ARM-based SoC Design [More Info] Joël Wanza Weloli, Bull | |
| 13:30 - 14:00 | Kilimandjaro 1 | Accelerating Silicon Diagnosis Using a Cell-Aware Flow [More Info] Nelly Feldman, STMicroelectronics | |
| 13:30 - 14:00 | Cervin | DDR System Simulation/Optimization of an Integrated MultiPHY IP [More Info] Déborah Cogoni, STMicroelectronics | |
| 13:30 - 14:00 | Kilimandjaro 3 | Detection & Management of Unwanted Logic in a Multi-Flop Synchronizer at Gate level using Spyglass-CDC [More Info] Amaury Brême, STMicroelectronics | |
| 13:30 - 14:00 | Mont-Blanc 1 | The Early Power Estimation Lottery: Increasing the Accuracy of Results in Order to Pick the Winning Number [More Info] Alessandro Nale, Nokia | |
| 14:00 - 14:30 | Cervin | STMicroelectronics-LIRMM: An Advanced Diagnosis Flow Using CustomSim for SRAMs [More Info] Tien-Phu HO, STMicroelectronics/LIRMM Patrice Loth, Synopsys | |
| 14:00 - 14:30 | Kilimandjaro 3 | Validation of Multi-Cycle Path Timing Exceptions in Simulation with Automatically Generated SystemVerilog Assertions [More Info] Akshaya Prashanthi Lakshmi Narayanan, Infineon Technologies AG | |
| 14:00 - 14:30 | Kilimandjaro 1 | ZOIX Evaluation in a STM32 Microcontroller [More Info] Martino Quattrocchi, STMicroelectronics | |
| 14:30 - 15:00 | Cervin | Custom Compiler Customization for ST Design Flows [More Info] Sébastien Mathieu, STMicroelectronics Eric Nercessian, STMicroelectronics | |
| 15:30 - 16:00 | Mont-Blanc 3 | Faster Timing Closure with Useful Skew using PrimeTime Clock ECO [More Info] Tarun Chawla, STMicroelectronics | |
| 15:30 - 16:00 | Mont-Blanc 1 | VC-LP : Not just for chips! [More Info] Ben Kerr, Toshiba America Electronic Components | |
| Verification & Virtual Prototyping | |||
| Thursday, June 22, 2017 | |||
| 10:45 - 11:15 | Kilimandjaro 3 | Performance Analysis of an ADAS System with Synopsys Platform Architect MCO [More Info] | |
| 11:15 - 11:45 | Kilimandjaro 3 | Platform Architect for HPC ARM-based SoC Design [More Info] Joël Wanza Weloli, Bull | |
| 11:45 - 12:15 | Kilimandjaro 3 | UPF3.0 for Early System-level Power Analysis [More Info] Bart Weuts, Synopsys | |
| 13:30 - 14:00 | Kilimandjaro 3 | Detection & Management of Unwanted Logic in a Multi-Flop Synchronizer at Gate level using Spyglass-CDC [More Info] Amaury Brême, STMicroelectronics | |
| 14:00 - 14:30 | Kilimandjaro 3 | Validation of Multi-Cycle Path Timing Exceptions in Simulation with Automatically Generated SystemVerilog Assertions [More Info] Akshaya Prashanthi Lakshmi Narayanan, Infineon Technologies AG | |
| 14:30 - 15:00 | Kilimandjaro 3 | Introduction to Reset Domain Crossings [More Info] Jérôme Avezou, Synopsys | |
| 15:30 - 17:00 | Kilimandjaro 3 | Increase Your Verification Productivity with VC Formal [More Info] Giovanni Auditore, STMicroelectronics Patrick Blestel, Synopsys | |
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