SNUG Canada 2017
 
Agenda
Friday, April 21, 2017

Use the pull downs below to filter by time, location or track:
General Sessions
Friday, April 21, 2017
9:00 am - 10:30 am
Signed/Sealed
Keynote - From Silicon to Software, Smartness Is Everything [More Info]
Speaker: Dr. Antun Domic, Chief Technology Officer, Synopsys
 
Implementation I
Friday, April 21, 2017
10:45 am - 11:30 am
Shakers
PrimeTime ECO Tutorial [More Info]
Speaker: Troy Epperly, Synopsys
11:30 am - 12:15 pm
Shakers
Scoring Big Points (Coverage, Cost, QoR) With Test Points. A DFT Hat Trick! [More Info]
Speaker: Don Dattani, Director, Cognitive Systems
1:15 pm - 2:00 pm
Shakers
An Object Oriented Framework to Process PrimeTime Reports [More Info]
Speaker: Aziz Mohammed, Senior Member of Technical Staff, Advanced Micro Devices
2:30 pm - 3:15 pm
Shakers
Galaxy RTL: Design Compiler Family 2016.12 Update [More Info]
Speaker: Cecilia Li, ViXS Systems
Speaker: Pervinder Trehan, Synopsys
3:30 pm - 5:00 pm
Shakers
Principles of Low Power Design Using UPF [More Info]
 
Implementation II
Friday, April 21, 2017
10:45 am - 11:30 am
Traders
Timing Closure and Design Compiler/ IC Compiler II Correlation in Advanced Nodes [More Info]
Speaker: John Vincent, Huawei Technologies Canada
11:30 am - 12:15 pm
Traders
Pipeline Register Planning [More Info]
Speaker: Bob Grozier, Synopsys
1:15 pm - 2:30 pm
Traders
IC Compiler II Technology Highlights [More Info]
Speaker: Mike Krause, Synopsys
2:30 pm - 3:15 pm
Traders
Evaluation of IC Compiler II Dynamic Power Optimization [More Info]
Speaker: Nour Radi, Advanced Micro Devices
3:30 pm - 5:00 pm
Traders
Floorplanning in IC Compiler II [More Info]
Speaker: Jim Lehmann, Synopsys
 
Networking Opportunities
Friday, April 21, 2017
7:45 am - 9:00 am
2nd Floor
Breakfast [More Info]
7:45 am - 5:00 pm
2nd Floor
Registration [More Info]
12:15 pm - 1:15 pm
Signed/Sealed
Networking Lunch
5:00 pm - 6:30 pm
Signed/Sealed
SNUG Pub and Awards Presentation [More Info]
 
User Content Reviewed by the Technical Committee
Friday, April 21, 2017
10:45 am - 11:30 am
Delivered
Terrestrial Verification Methodology: A Down-to-Earth Approach to Developing a UVM VIP [More Info]
Speaker: Bryan Morris, Senior ASIC Verification Engineers, Ciena
10:45 am - 11:30 am
Traders
Timing Closure and Design Compiler/ IC Compiler II Correlation in Advanced Nodes [More Info]
Speaker: John Vincent, Huawei Technologies Canada
10:45 am - 11:30 am
Deciders
Use of Verification Point Tools [More Info]
Speaker: Michael Thompson, IC Verification Engineer, Rianta Solutions
Speaker: Thomas Zboril, Huawei Technologies Canada
11:30 am - 12:15 pm
Shakers
Scoring Big Points (Coverage, Cost, QoR) With Test Points. A DFT Hat Trick! [More Info]
Speaker: Don Dattani, Director, Cognitive Systems
11:30 am - 12:15 pm
Deciders
Speedup Silicon Issue Debug with VC Formal [More Info]
Speaker: Wayne Yun, Principle Member of Technical Staff, Advanced Micro Devices
11:30 am - 12:15 pm
Delivered
UVM Error Injection Using a Two-Phase Slave Sequence [More Info]
Speaker: Mona Beimers, Senior Staff Verification Engineer, Xilinx
1:15 pm - 2:00 pm
Shakers
An Object Oriented Framework to Process PrimeTime Reports [More Info]
Speaker: Aziz Mohammed, Senior Member of Technical Staff, Advanced Micro Devices
3:30 pm - 4:15 pm
Delivered
Perplexing Parameter Permutation Problems? Immunize Your Testbench [More Info]
Speaker: Alex Melikian, Principal Verification Consultant, Verilab
3:30 pm - 4:15 pm
Deciders
Using Verdi to Generate vi and emacs Tagging Databases [More Info]
Speaker: David Carson, Senior Staff Engineer, Huawei Technologies Canada
4:15 pm - 5:00 pm
Deciders
Formal Coverage for Verification Sign-Off [More Info]
Speaker: Roger Sabbagh, VP of Applications Engineering, Oski Technology
Speaker: Anders Nordstrom, Synopsys
4:15 pm - 5:00 pm
Delivered
UVM Architecture for Performance: Go Hierarchical! [More Info]
Speaker: Paul Lungu, Verification Architect, Ciena
 
Verification I
Friday, April 21, 2017
10:45 am - 11:30 am
Delivered
Terrestrial Verification Methodology: A Down-to-Earth Approach to Developing a UVM VIP [More Info]
Speaker: Bryan Morris, Senior ASIC Verification Engineers, Ciena
11:30 am - 12:15 pm
Delivered
UVM Error Injection Using a Two-Phase Slave Sequence [More Info]
Speaker: Mona Beimers, Senior Staff Verification Engineer, Xilinx
1:15 pm - 2:15 pm
Delivered
VCS Performance Innovations - Fine-Grained Parallelism and More! [More Info]
Speaker: Kiran Maiya, Synopsys
2:15 pm - 3:15 pm
Delivered
Boosting Debug Productivity – Practical Applications of Verdi Debug Innovations [More Info]
Speaker: Myles Glisson, Synopsys
3:30 pm - 4:15 pm
Delivered
Perplexing Parameter Permutation Problems? Immunize Your Testbench [More Info]
Speaker: Alex Melikian, Principal Verification Consultant, Verilab
4:15 pm - 5:00 pm
Delivered
UVM Architecture for Performance: Go Hierarchical! [More Info]
Speaker: Paul Lungu, Verification Architect, Ciena
 
Verification II
Friday, April 21, 2017
10:45 am - 11:30 am
Deciders
Use of Verification Point Tools [More Info]
Speaker: Michael Thompson, IC Verification Engineer, Rianta Solutions
Speaker: Thomas Zboril, Huawei Technologies Canada
11:30 am - 12:15 pm
Deciders
Speedup Silicon Issue Debug with VC Formal [More Info]
Speaker: Wayne Yun, Principle Member of Technical Staff, Advanced Micro Devices
1:15 pm - 2:15 pm
Deciders
Introduction to CDC and Reset Checks for FPGA and ASIC Designers [More Info]
Speaker: Gregory Milano, Synopsys
2:15 pm - 3:15 pm
Deciders
Speeding Up Verification Closure using Formal Techniques [More Info]
Speaker: Tushar Parikh, Synopsys
3:30 pm - 4:15 pm
Deciders
Using Verdi to Generate vi and emacs Tagging Databases [More Info]
Speaker: David Carson, Senior Staff Engineer, Huawei Technologies Canada
4:15 pm - 5:00 pm
Deciders
Formal Coverage for Verification Sign-Off [More Info]
Speaker: Roger Sabbagh, VP of Applications Engineering, Oski Technology
Speaker: Anders Nordstrom, Synopsys