| 8:00 am - 9:20 am | Grand Ballroom Foyer | | Registration/Breakfast [More Info] |
| 9:20 am - 9:30 am | Sky Ballroom | | Welcome [More Info] |
| 9:30 am - 10:30 am | Sky Ballroom | | Keynote -"The Future of Mobility Autonomous Vehicles" [More Info]
Mr Chee Seong Chua, President & Managing Director, Infineon Technologies Asia Pacific Pte Ltd
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| 10:35 am - 11:00 am | Grand Ballroom 3 | | Design Verification of ISO26262 Automotive IP using Synopsys ZO1X [More Info]
Wai Meng Looi, Mediatek
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| 10:35 am - 11:00 am | Grand Ballroom 1 | | Easytime: A Forward-Thinking Instrument to Analyze Static Timing Reports [More Info]
Deep Yap, Mediatek
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| 10:35 am - 11:00 am | Grand Ballroom 2 | | Enhanced Design Efficiency for Huge High Performance SoCs to Market with Synopsys Design Platform [More Info]
Vy Tran, Renesas
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| 10:35 am - 11:00 am | The Boardroom | | Improving Pattern Matching Accuracy with Duplex Pattern Masking [More Info]
Yongfu Li, GLOBALFOUNDRIES
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| 11:00 am - 11:25 am | Grand Ballroom 2 | | Accurate Pipeline Stage Calculation With Timing Based Location Optimization [More Info] |
| 11:00 am - 11:25 am | Grand Ballroom 1 | | Accurate Power Consumption Prediction and Optimizations using Synopsys Tool Suites [More Info]
Govindraya Prabhu S, Infineon
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| 11:00 am - 11:25 am | Grand Ballroom 3 | | SoC Prototyping Challenges and Solutions [More Info] |
| 11:00 am - 11:25 am | The Boardroom | | Verilog-AMS Asserts & Drivers to Improve SoC Mixed Signal Simulation Accuracy and Performance for the Safety Audit Compliance [More Info]
Ridhi Saini, Infineon
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| 11:25 am - 12:05 pm | Grand Ballroom 2 | | Achieving Best QOR and Fastest Time to Results with Synopsys' Fusion Platform [More Info]
Arvind Narayanan, Synopsys
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| 11:25 am - 12:05 pm | Grand Ballroom 1 | | Design Compiler Recent Technology Enhancements, QoR Improvements & Roadmap/Customer Success Experience Sharing [More Info]
Hari Narayan Shanmugam, Synopsys
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| 11:25 am - 12:05 pm | The Boardroom | | Physically-Aware Simulation and Electrical Analysis with Fusion Technology [More Info] |
| 11:25 am - 12:05 pm | Grand Ballroom 3 | | Whats New in Emulation and Why: Technology Trends and Drivers in Emulation [More Info]
Sivaprasad Acharaya, Synopsys
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| 12:05 pm - 1:15 pm | Sky Ballroom | | Networking Lunch [More Info] |
| 1:20 pm - 2:00 pm | Grand Ballroom 2 | | IC Compiler II Technology Update [More Info]
Arvind Narayanan, Synopsys
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| 1:20 pm - 2:00 pm | The Boardroom | | AMS Simulation, Post Layout Simulation, Characterization Update [More Info]
Xi Jiang, Synopsys
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| 1:20 pm - 2:00 pm | Grand Ballroom 1 | | Signoff Power Analysis Driven PrimeTime ECO for Best PPA - Accelerated by Machine Learning [More Info]
Vivek Ghante, Synopsys
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| 1:20 pm - 2:00 pm | Grand Ballroom 3 | | Tackling SystemVerilog and UVM Testbench Debug Challenges Interactive Debug with Verdi and VCS / Customer (Renesas) Success Experience Sharing [More Info]
Pham Trung Kien, Renesas
Eugene Ho, Synopsys
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| 2:00 pm - 2:25 pm | Grand Ballroom 1 | | A Holistic Methodology of Zero-cycle Timing Path for Latency Reduction [More Info]
Simin Xu, Xilinx
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| 2:00 pm - 2:25 pm | The Boardroom | | A Practical Library Qualification Methodology with Interconnect Parasitic Consideration in an Automated Correlation Test Cases [More Info]
Lain Shen Tyah, eAsic
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| 2:00 pm - 2:25 pm | Grand Ballroom 2 | | Power Optimization for ASICs: Using Custom Low Power Flops [More Info]
Tinh Ho, eSilicon
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| 2:00 pm - 2:25 pm | Grand Ballroom 3 | | Shift-left Verification for Large Scale R-Car SoC with Formal Verification Methodology [More Info]
Hai Nguyen, Renesas
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| 2:25 pm - 2:50 pm | Grand Ballroom 2 | | Ballooned Placement for Datapath Registers [More Info] |
| 2:25 pm - 2:50 pm | Grand Ballroom 1 | | Best Practices in Synthesis Area Recovery Using optimize_netlist [More Info]
Chin Leong Lou, ChipGlobe
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| 2:25 pm - 2:50 pm | Grand Ballroom 3 | | Case Studies: Efficient Abstract Validation for Catching CDC Bugs in SoC [More Info] |
| 2:25 pm - 2:50 pm | The Boardroom | | IC Compiler II - Custom Compiler Co-Design with Fusion Technology / Customer (Renesas) Success Experience Sharing [More Info]
Choo Kiong Then, Synopsys
Thien Tran Vuong Trong, Renesas
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| 2:50 pm - 3:30 pm | Grand Ballroom 3 | | Comprehensive SDC-based Clock Domain Crossing Verification [More Info]
Ajay Rana, Synopsys
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| 2:50 pm - 3:30 pm | Grand Ballroom 2 | | Accelerate Time-to-Market with RedHawk Analysis Fusion and Maximize Design Robustness [More Info]
Bryan Chen, Synopsys
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| 2:50 pm - 3:30 pm | Grand Ballroom 1 | | CCD Technology Highlight/Customer CCD Experience Sharing [More Info]
Anusha Reddy Sindhwala, Synopsys
Phuoc Le Ngoc Vu, Renesas
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| 2:50 pm - 3:30 pm | Grand Ballroom 3 | | Test Bench Solution and Verification IP for Designing Artificial Intelligence SoCs [More Info]
Satyapriya Acharya, Synopsys
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| 3:30 pm - 4:00 pm | Grand Ballroom Foyer | | Tea Break [More Info] |
| 4:00 pm - 5:00 pm | Sky Ballroom | | Vision Address - The Pace of Innovation [More Info]
Don Chan, Senior Vice President, Design Group, Synopsys
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| 5:00 pm - 5:30 pm | Sky Ballroom | | Best Paper Awards & Lucky Draw [More Info] |
